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High-Speed
Links
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M. Brownlee,
P. Hanumolu, K. Mayaram,and U. Moon, "A
0.5 to 2.5-GHz PLL with fully differential supply regulated
tuning," IEEE J. Solid-State Circuits, pp.
2720-2728, Dec. 2006.
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P. Hanumolu,
M. Kim, G. Wei, and U. Moon, "A
1.6Gbps digital clock and data recovery circuit," IEEE
Custom Int. Circuits Conf., pp. 603-606, Sep. 2006.
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P. Hanumolu,
G. Wei, and U. Moon, "A
wide tracking range 0.2-4Gbps clock and data recovery circuit,"
IEEE Symp. VLSI Circuits, pp. 88-89, Jun. 2006.
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P. Hanumolu,
V. Kratyuk, G. Wei, and U. Moon, "A
sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter,"
IEEE Symp. VLSI Circuits, pp. 92-93, Jun. 2006.
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V. Kratyuk,
P. Hanumolu, K. Ok, K. Mayaram, and U. Moon, "A
digital PLL with a stochastic time-to-digital converter,"
IEEE Symp. VLSI Circuits, pp. 38-39, Jun. 2006.
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M. Brownlee,
P. Hanumolu, K. Mayaram,and U. Moon, "A
0.5 to 2.5GHz PLL with fully differential supply-regulated tuning,"
IEEE Int. Solid-State Circuits Conf., pp. 588-589,
Feb. 2006.
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P. Hanumolu,
G. Wei, and U. Moon, "Equalizers
for high-speed serial links," Int. J. High Speed
Elec. Syst., vol. 15, no. 2, pp. 429-458, Jun. 2005.
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P. Hanumolu,
M. Brownlee, K. Mayaram, and U. Moon, "Analysis
of charge-pump phased-locked loops," IEEE Trans.
Circuits Syst. I, pp. 1665-1674, Sep. 2004.
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P. Hanumolu,
B. Casper, R. Mooney, G. Wei, and U. Moon, "Analysis
of PLL clock jitter in high-speed serial links," IEEE
Trans. Circuits Syst. II, pp. 879-886, Nov. 2003.
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M. Brownlee,
P. Hanumolu, U. Moon, and K. Mayaram, "The effect of power
supply noise on ring oscillator phase noise," IEEE
Northeast Workshop Circuits Syst., pp. 225-228, Jun. 2004.
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P. Hanumolu,
B. Casper, R. Mooney, G. Wei, and U. Moon, "Jitter
in high-speed serial and parallel links," IEEE
Int. Symp. Circuits Syst., vol. IV, pp. 425-428, May 2004.
Data
Converters
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G. Ahn,
P. Hanumolu, M. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita,
K. Takasuka, G. Temes, and U. Moon, "A
12b 10MS/s pipelined ADC using reference scaling,"
IEEE Symp. VLSI Circuits, pp. 272-273, Jun. 2006.
- M. Kim,
G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes,
and U. Moon, "A
0.9V 92dB double-sampled switched-RC delta-sigma audio ADC,"
IEEE Symp. VLSI Circuits, pp. 200-201, Jun. 2006.
Filters
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P. Kurahashi,
P. Hanumolu, G. Temes, and U. Moon, "A
0.6V highly linear Switched-R-MOSFET-C filter," IEEE
Custom Int. Circuits Conf., pp. 833-836, Sep. 2006.
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G. Vemulapalli,
P. Hanumolu, Y. Kook, and U. Moon, "A
0.8V, accurately tuned, linear continuous-time filter,"
IEEE J. Solid-State Circuits, pp. 1972-1977, Sep. 2005.
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G. Vemulapalli,
P. Hanumolu, and U. Moon, "A
0.8V accurately-tuned continuous-time filter," IEEE
Custom Int. Circuits Conf., pp. 45-48, Oct. 2004.
Miscellaneous
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V. Kratyuk,
P. Hanumolu, U. Moon, and K. Mayaram, "A
low spur fractional-N frequency synthesizer architecture,"
IEEE Int. Symp. Circuits Syst., pp. 2807-2810, May
2005.
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T. Wu,
P. Hanumolu, U. Moon, and K. Mayaram, "An
FMDLL based dual-loop frequency synthesizer for 5GHz WLAN applications,"
IEEE Int. Symp. Circuits Syst., pp. 3986-3989, May
2005.
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N. Talebbeydokhti,
P Hanumolu, P. Kurahashi, and U. Moon, "Constant
transconductance bias circuit with an on-chip resistor,"
IEEE Int. Symp. Circuits Syst., pp. 2857-2860, May
2006.
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