Mixed-Mode Integrated Circuits Group

    Pavan Kumar Hanumolu
    Assistant Professor
    Oregon State University
Publications
 

Journal Papers    Conference Papers

  1. A. Arakali, S. Gondi, and P. Hanumolu, "Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture," IEEE J. Solid-State Circuits, to appear, 2009.
     
  2. N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, "A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback," IEEE J. Solid-State Circuits, to appear, 2009.
     
  3. M. Kim, P. Hanumolu, and U. Moon, "A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking scheme," IEEE J. Solid-State Circuits, to appear, 2009.
     
  4. V. Kratyuk, P. Hanumolu, K. Mayaram, and U. Moon, "A digital PLL with stochastic time-to-digital converter," IEEE Trans. Circuits Syst. I, to appear, 2009.
     
  5. I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Automated design and optimization of low-noise oscillators," IEEE Trans. Computer-Aided Design, pp. 609-622, May 2009.
     
  6. T. Wu, P. Hanumolu, K. Mayaram, and U. Moon, "Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers," IEEE J. Solid-State Circuits, pp. 427-435, Feb. 2009.
     
  7. I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity analysis for oscillators," IEEE Trans. Computer-Aided Design, pp. 1521-1534, Sep. 2008.
     
  8. M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, "A 0.9V 92dB doubled-sampled switched-RC delta-sigma audio ADC," IEEE J. Solid-State Circuits, pp. 1195-1206, May 2008.
     
  9. P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon, "A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter," IEEE J. Solid-State Circuits, pp. 414-424, Feb. 2008.
     
  10. P. Hanumolu, G. Wei, and U. Moon, "A wide-tracking range clock and data recovery circuit,", IEEE J. Solid-State Circuits, pp. 425-439, Feb. 2008.
     
  11. P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon, "Design of low-voltage highly linear switched-R-MOSFET-C filters," IEEE J. Solid-State Circuits, pp. 1699-1709, Aug. 2007.
     
  12. V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy," IEEE Trans. Circuits Syst. II, vol. 54, no. 3, pp. 247-251, Mar. 2007.
     
  13. V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "Frequency detector for fast frequency lock of digital PLLs," Electron. Lett., vol. 43, no. 1, pp. 13-14, Jan. 4, 2007.
     
  14. M. Brownlee, P. Hanumolu, K. Mayaram, U. Moon, "A 0.5-GHz to 0.5-GHz PLL with fully differential supply regulated tuning," IEEE J. Solid-State Circuits, pp. 2720-2728, Dec. 2006.
     
  15. P. Hanumolu, G. Wei, and U. Moon, "Equalizers for high-speed serial links," Int. J. High Speed Elec. Syst., vol. 15, no. 2, pp. 429-458, Jun. 2005.
     
  16. G. Vemulapalli, P. Hanumolu, Y. Kook, and U. Moon, "A 0.8V, accurately tuned, linear continuous-time filter," IEEE J. Solid-State Circuits, pp. 1972-1977, Sep. 2005.
     
  17. P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, "Analysis of charge-pump phased-locked loops," IEEE Trans. Circuits Syst. I, pp. 1665-1674, Sep. 2004.
     
  18. P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon, "Analysis of PLL clock jitter in high-speed serial links," IEEE Trans. Circuits Syst. II, pp. 879-886, Nov. 2003.

Conference Papers    Journal Papers

  1. O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu, and U. Moon, "A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC," IEEE Symp. VLSI Circuits, to appear, Jun. 2009.
     
  2. M. Kim, V. Kratyuk, P. Hanumolu, G. Ahn, S. Kwon, and U. Moon, "An 8mW 10b 50MS/s pipelined ADC using 25dB opamp," IEEE Asian Solid-State Circuits Conf., pp. 49-52, Nov. 2008.
     
  3. D. Gubbins, B. Lee, P. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC," IEEE Custom Int. Circuits Conf., pp. 21-24, Sep. 2008.
     
  4. A. Arakali, S. Gondi, and P. Hanumolu, "A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB," IEEE Custom Int. Circuits Conf., pp. 443-446, Sep. 2008.
     
  5. A. Agarwal, P. Hanumolu, and G. Wei, "An 8x5 Gb/s source-synchronous receiver with clock generator phase error correction," IEEE Custom Int. Circuits Conf., pp. 459-462, Sep. 2008.
     
  6. I. Vytyaz, J. Carnes, T. Wu, P. Hanumolu, U. Moon, and K. Mayaram, "Noise tolerant oscillator design using perturbation projection vector analysis," IEEE Custom Int. Circuits Conf., pp. 695-698, Sep. 2008.
     
  7. P. Kurahashi, P. Hanumolu, and U. Moon, "A 1V downconversion filter using duty-cycle controlled bandwidth tuning," IEEE Custom Int. Circuits Conf., pp. 707-710, Sep. 2008.
     
  8. A. Arakali, S. Gondi, N. Talebbeydokthi, and P. Hanumolu, "Supply-noise mitigation techniques in phase-locked loops," IEEE European Solid-State Circuits Conf., pp. 374-377, Sep. 2008.
     
  9. I. Vytyaz, P. Hanumolu, U. Moon, and K. Mayaram, "Periodic steady-state analysis augmented with design equality constraints," Design Auto. Test Europe (DATE), pp. 312-317, Mar. 2008.
     
  10. A. Agarwal, P. Hanumolu, and G. Wei, "An 8x3.2Gbps parallel receiver with collaborative timing recovery," IEEE Int. Solid-State Circuits Conf., pp. 468-469, Feb. 2008.
     
  11. J. Carnes, I. Vytyaz, P. Hanumolu, K. Mayaram, and U. Moon, "Design and analysis of noise tolerant ring oscillators using Maneatis delay cells," IEEE Int. Conf. Elec. Circuits Syst., pp. 494-497, Dec. 2007.
     
  12. I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity analysis for oscillators," Int. Conf. Computer-Aided Design (ICCAD), pp. 458-463, Nov. 2007.
     
  13. N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, " A 1.8V 36mW 11bit 80MS/s pipelined ADC using capacitor and opamp sharing," IEEE Asian Solid-State Circuits Conf., pp. 240-243, Nov. 2007.
     
  14. G. Ahn, M. Kim, P. Hanumolu, and U. Moon, "A 1V 10b 30MSPS switched-RC pipelined ADC," IEEE Custom Int. Circuits Conf., pp. 325-328, Sep. 2007.
     
  15. M. Brownlee, P. Hanumolu, and U. Moon, "A 3.2Gb/s oversampling CDR with improved jitter tolerance," IEEE Custom Int. Circuits Conf., pp. 353-356, Sep. 2007.
     
  16. V. Kratyuk, P. Hanumolu, K. Mayaram, and U. Moon, "A 0.6GHz to 2GHz digital PLL with wide tracking range," IEEE Custom Int. Circuits Conf., pp. 305-308, Sep. 2007.
     
  17. P. Hanumolu, G. Wei, U. Moon, and K. Mayaram, "Digitally-enhanced phase-locking circuits," IEEE Custom Int. Circuits Conf., pp. 361-368, Sep. 2007.
     
  18. T. Wu, P. Hanumolu, K. Mayaram, and U. Moon, "A 4.2 GHz PLL frequency synthesizer with an adaptively tuned coarse loop," IEEE Custom Int. Circuits Conf., pp. 547-550, Sep. 2007.
     
  19. P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon, "A 0.6V highly linear Switched-R-MOSFET-C filter," IEEE Custom Int. Circuits Conf., pp. 833-836, Sep. 2006.
     
  20. P. Hanumolu, M. Kim, G. Wei, and U. Moon, "A 1.6Gbps digital clock and data recovery circuit," IEEE Custom Int. Circuits Conf., pp. 603-606, Sep. 2006.
     
  21. V. Kratyuk, P. Hanumolu, K. Ok, K. Mayaram, and U. Moon, "A digital PLL with a stochastic time-to-digital converter," IEEE Symp. VLSI Circuits, pp. 38-39, Jun. 2006.
     
  22. P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon, "A sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter," IEEE Symp. VLSI Circuits, pp. 92-93, Jun. 2006.
     
  23. P. Hanumolu, G. Wei, and U. Moon, "A wide tracking range 0.2-4Gbps clock and data recovery circuit," IEEE Symp. VLSI Circuits, pp. 88-89, Jun. 2006.
     
  24. G. Ahn, P. Hanumolu, M. Kim, S. Takeuchi1, T. Sugimoto1, K. Hamashita1, K. Takasuka1, G. Temes, and U. Moon, "A 12b 10MS/s pipelined ADC using reference scaling," IEEE Symp. VLSI Circuits, pp. 272-273, Jun. 2006.
     
  25. M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, "A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC," IEEE Symp. VLSI Circuits, pp. 200-201, Jun. 2006.
     
  26. M. Kim, P. Hanumolu, and U. Moon, "A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking," IEEE Symp. VLSI Circuits, pp. 60-61, Jun. 2006.
     
  27. N. Talebbeydokhti, P Hanumolu, P. Kurahashi, and U. Moon, "Constant transconductance bias circuit with an on-chip resistor," IEEE Int. Symp. Circuits Syst., pp. 2857-2860, May 2006.
     
  28. M. Brownlee, P. Hanumolu, K. Mayaram,and U. Moon, "A 0.5 to 2.5GHz PLL with fully differential supply-regulated tuning," IEEE Int. Solid-State Circuits Conf., pp. 588-589, Feb. 2006.
     
  29. V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "A low spur fractional-N frequency synthesizer architecture," IEEE Int. Symp. Circuits Syst., pp. 2807-2810, May 2005.
     
  30. T. Wu, P. Hanumolu, U. Moon, and K. Mayaram, "An FMDLL based dual-loop frequency synthesizer for 5GHz WLAN applications," IEEE Int. Symp. Circuits Syst., pp. 3986-3989, May 2005.
     
  31. G. Vemulapalli, P. Hanumolu, and U. Moon, "A 0.8V accurately-tuned continuous-time filter," IEEE Custom Int. Circuits Conf., pp. 45-48, Oct. 2004.
     
  32. M. Brownlee, P. Hanumolu, U. Moon, and K. Mayaram, "The effect of power supply noise on ring oscillator phase noise," IEEE Northeast Workshop Circuits Syst., pp. 225-228, Jun. 2004.
     
  33. P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon, "Jitter in high-speed serial and parallel links," IEEE Int. Symp. Circuits Syst., vol. IV, pp. 425-428, May 2004.