MOSIS NDA

This is an important step to obtain access to tsmc 0.18um pdk for the class

To access tsmc 0.18um pdk, mosis requires all the users to sign a Non-Disclosure Agreement (NDA). Please print a copy of the MOSIS NDA form, sign and submit to Prof. Moon to be added to the pdk user list.

EXAMPLE:
LAYOUT OF AN INVERTING AMPLIFIER

This example will help you to create a layout for the inverter you designed in the first example. It will go over the Virtuoso layout tool and how to layout mosfets, resistors, and capacitors in our process. There are many considerations to take into account when deciding how to do a layout. This is NOT an example on layout techniques, but more of a generalized example to help get you farmiliar with Virtuoso and laying-out some basic components.

The following picture shows a layout for the inverting amplifier, ready for extracting. The next section explains how to make each of the separate components in Virtuoso.

Simple inverting amplifier
Figure 1: Layout example.
You may see a license warning about Virtuoso_Layout_Suite_L in the CIW window. You may ignore this. That just means the basic license for Layout L is unavailable, and another version called Virtuoso_Layout_Suite_GXL will be used.

1. Create a new cell, where you will layout the inverter:

To open a new design, select the following from the Library Manager:
layoutcell
Figure 2: New Layout Cellview.
A layout window opens. Also, the Palette window opens at the lefthand side of the screen. Palette window offers various selection and visibility options which can be used to highlight or select only specific layers in the layout. Feel free to explore the AV, NV, AS and NS options on the top of the Palette window. The Objects subwindow can be used to highlight or select various objects in the layout such as instances, shapes, vias, etc..
palette
Figure 3: Palette Window.

Make sure that the grid size for the layout is set to 0.005um. This is a really important step. Violating the minimum grid size can result in off-grid errors in the later stages.
To set the grid size, choose Options->Display
Set X snap spacing and Y snap spacing to 0.005

gridsize
Figure 4: Setting the grid size .
Designing the layout of a circuit consists of selecting the desired layers from the Palette Window and using commands from the following list (keyboard shortcut keys are in brackets):

Creating shapes Create->Rectangle [r]
Create->Path [p]
Editing shapes Edit->Move [m]
Edit->Stretch [s]
Edit->Copy [c]
Edit->Delete [del]
Edit->Properties [q]
Edit->Undo [u]
Edit->Redo [U]
Measuring distances Misc->Ruler [k]
Misc->Clear Rulers [K]
Window commands Zoom In [z]
Zoom In by 2 [^z]
Zoom Out By 2 [Z]
Fit All [f]
Redraw [^r]
Other commands Gravity On/Off[g]
Display levels (0-20) [F]
Display levels (0-0) [^f]

2. Laying-out the components for your circuit:

For this inverter we will need to layout an nmos transistor, a resistor, and a capacitor. The following sections will describe how to access the layout of these components from the pdk and how to access the terminals for routing. SOme of these steps are very similar to the schematic example.

2.1 Layout of MOSFETs:

When laying-out MOSFETs, we actually have preset cells which we can draw from.
From the Layout window:

When making MOSFETs you can create a single transistor, or use fingers or multipliers to create multiple transistors at once. Fingers makes transistors which are connected in series, multipliers create transistors which are connected in parallel. For our layout example we will be using fingers to make multiple transistors which will be equivalent to one really wide transistor. However, if transistors have to be matched, multipliers are preferred.