Mission Statement:
How do we design new circuit architectures in deep submicron technologies that take advantage of its benefits, namely ubiquitous transistors, increased transistor performance, and system-on-a-chip possibilities--while compensating for its growing disadvantages, such as process variation, power consumption, inaccurate parasitic/device modeling, and increased design time/cost?
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Biography
Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007. Since 2006, he has been an assistant professor at Oregon State University.As an undergraduate at Berkeley, he worked on the Dynamic-Voltage Scaled Microprocessor System for the Infopad project. In 1998, he was a design engineer at Datapath Systems (now LSI), where he worked on an automated generation of a low-power, digital standard cell library for a xDSL analog front-end. In 2003 he was a research intern at Velio Communications (now Rambus) investigating low-jitter, 10GHz clock synthesis techniques. In 2004, he worked as a consultant at Telegent Systems, where he analyzed low-phase noise VCOs for analog, mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In 2007, he was a visiting professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (Beijing, China), with his lab working in collaboration with ICT on high-speed, low-power serial link transceivers in deep submicron CMOS.
His interests are in the design and implementation of new architectures for mixed signal circuits in deep submicron CMOS. In high speed serial links, his interests include the design of low power, high data rate, parallel I/O's; and the implementation of 20+ GHz, 4-5 bit low power ADCs for limited bandwidth channels. In RF circuits, his research revolves around the design of reconfigurable, self-healing RF transceivers to compensate for process variation in future CMOS technologies; Impulse-Radio, Ultrawideband RF Transceivers.