Welcome to Shih-Lien Lu's Home Page


I am currently a Principal Researcher and lead the Oregon Microarchitecture Lab at Intel's MTG/CTG. I am serving as an adjunct faculty for OSU. My public discription at Intel is here.

PREVIOUS RESEARCH INTERESTS

  • CounterFlow Pipeline Processor Research(CFPP)
  • MIRROR of:CounterFlow Pipeline Processor Research(CFPP)
  • Selftimed Circuits and Systems Design
  • VLSI Systems
  • Computer Arithmetic
  • Computer Architecture

    Acknowledgement

    GRADUATE STUDENTS

  • PhD students
  • MS students
  • A very good article on how to be a good advisor/graduate-student.

    CLASSES

  • ECE679-FPGA Design Using VHDL
  • ECE679-Computer Memory Systemss
  • ECE474/574-VLSI Systems Design
  • ECE577-Computer Arithmetic
  • ECE679-Asynchronous Logic ( OCATE
  • ECE473/573-Microprocessor Based Design

    HOW TO CONTACT ME

    (sllu at eecs DOT oregonstate dot edu)
    USPS Mail: Dept. of ECE, OSU, Corvallis, OR 97331

    MISC

    ASPLOS Workshop on Architecting Memory Technologies

    Church I attend.
    solution I found for the Bible books puzzle
    My netscape bookmarks.
    Click here to see my picture. Click here to see my resume.

    You are the visitor number Since 4/19/1996


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