Workshop on Architecting Memory Technologies


We expect a dramatic shift in the memory system driven by the growing bandwidth mismatch between memory and CPU, the need to reduce power consumption of the system and the availability of emerging alternative memory technologies.

On the technology side, there are many technologies aimed at evolving high density memory: embedded DRAM, Thyristor_RAM, Ferroelectric-RAM, Resistive-RAM, etc. Many of these could be potentially embedded on the CPU die or in the same package with near-cache-access speeds. From the other end, FLASH based solid state disks (SSDs) have gained much momentum recently as the desired storage technology. Other non-volatile new memory devices such as Phase Change Memory (PCM) and Spin-Torque Transfer Magnetic RAM (STT MRAM) are rapidly gaining attention as well.

Power consumption continues to be a very important parameter to optimize. Currently a typical DDR-type DIMM consumes more than 3W of power when active. A large system with many DIMMs will consume many watts. There are new link interfaces being developed that will reduce the I/O power drastically. However it is difficult to overcome the initial cost momentum.

On the memory speed side, we are seeing miss penalties from the last level cache reach hundreds of cycles (e.g., a 150ns average memory access time is 600 cycles for a 4-GHz CPU). This is in the same range as the page fault penalties of early virtual memory systems of the 1960s in terms of CPU cycles. This miss penalty is limiting the performance improvement of the system. Moreover the current standard interface to DRAM limits the bandwidth growth without throwing the power consumption requirement out of the wall.

Minor evolutionary improvements can no longer satisfy the performance and power needs of future systems Moreover, simply using new technologies as replacements of existing hierarchy or adding new levels into the hierarchy may not be the most desirable approach. Instead we ask ourselves:

  • What will be the right memory system in the coming ten years?
  • What are the major research challenges that must be overcome to create this memory system?
  • What will be the impacts to the computing platform and software in light of the new memory system?

    The workshop was held on 3/14/2010 at Pittsburg PA in conjunction with ASPLOS 2010.

    An introduction was given by Shih-Lien Lu from Intel and Panlists' slides can be found below:

  • Shih-Lien Lu, Intel Labs
  • Professor Mattan Erez, University of Texas at Austin
  • Professor Bruce Jacob, University of Maryland
  • Professor Hsien-Hsin Lee, Georgia Tech University
  • Professor Onur Mutlu, Carnegie Mellon University
  • Professor Yuan Xie, Pennsylvania State University