ECE474/574 VLSI Systems Design

Department of Electrical and Computer Engineering,
Oregon State University

Welcome to VLSI Systems Design course homepage! This page provides access to class info outside of the classroom.

This page is currently under construction.....

Annoucements

Course Information

Course Description

This class is an introduction to VLSI Systems design. It will give you a feeling for the basic principles that govern the design of large scale digital ICs. Advancement in IC technology has been fueling the growth in many areas including computer and communicaiton for the past few decades. For example, microprocessor has grown from a few thousand transistors to more than 20 millions in 1999. It's performance has risen exponentially. Our emphasis will be on the overall picture of the methodology used in designing a complex IC chip. We will attempt to cover several levels of abstraction within the system. However due to time limitation we will not be able to go into fine details and hopefully you will explore them further in other classes.

Prerequisites

This class will assume a background in digital logic (ECE271) and computer organization (ECE375), and some understanding of RC circuits (ECE323). The class will also use a number of CAD tools that run on the Unix workstations. You will learn how to use computer-assisted design (CAD) tools - magic and irsim for layout, HSPICE for circuit simulation, and the Mentor VHDL functional simulator (based on ModeTech) and the logic synthesis tools Leonardo (based on Exemplar). Familiarity with Unix System is assumed. A set of tutorials on Magic can be found at this directory in ps format.

Enrollment limited to 80 students.

Instructors

Shih-Lien Lu , sllu@ece.orst.edu, 541-737-2980 (office), Office Hours: Thursdays 3:00-5.
Roger Traylor , traylor@ece.orst.edu, 541-737-2975 (office), Office Hours: TBA

TA's

Ryan Larson , larsonry@ece.orst.edu Office Hours: TBA

Lectures

MWF 10:00-11:00 ECE106
See the schedule for more information.

Lecture Notes

Lecture Note on Testing

Lecture Note on Timing

Problem Sets and Lab Assignments

(35% of final grade) Some combination of lab work and home work. Problems will be too long to complete the night before due, so please plan accordingly.

HW #1

HW #1 solution

New Block diagram for HW #1

Almost completed RTL descriptions of all OSU8 instructions!

HW #2

Lab #4

TAS Project Information and Roger's Labs (New)

TAS Requirments Document

Lab 1: Getting Setup to Run Mentor Graphics Software

Lab 2: Writing, Compiling, Debugging, and Simulating VHDL

Lab 3: Hierarchical structures in VHDL

Lab 4: Using VHDL for State Machines

Lab 5: Synthesis Using VHDL

Dofiles for testing TAS

Synthesis instructions for TAS

(30% of final grade) Student will work in group to complete, through VHDL simulation and synthesis a final project design and to create a web page documenting the design.

Exams

(35% of final grade) Two 45-minute in-class quizzes (each worth 7.5% of final grade). Meant to be "easy" if you've been keeping up with the homework and the lectures, though they will require that you can work quickly. One final exam (20% of final grade).