Shih-Lien L. Lu, Associate Professor (on Industrial Leave)

Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR 97331

(541)737-2980 (541)737-1300 (fax) email: sllu@ece.orst.edu web address: http://www.ece.orst.edu/~sllu
EDUCATION:

  • Ph.D. Computer Science, University of California, Los Angeles, 1991
  • M.S. Computer Science, University of California, Los Angeles, 1984
  • B.S. Electrical Engineering and Computer Science, University of California, Berkeley, 1980


    EXPERIENCE:

  • 6/1999-present, Senior Staff Researcher
    Microcomputer Research Laboratory, Intel Corp., Hillsboro, OR
    Research in memory architecture.
  • 8/1997-6/1998, Visiting Faculty
    Microcomputer Research Laboratory, Intel Corp., Hillsboro, OR
    Low Voltage, Low Power Circuit Technology Research.
  • 6/1996-9/1996 Summer Visiting Faculty
    Microcomputer Research Laboratory, Intel Corp., Hillsboro, OR
    Microarchitecture simulator and instruction scheduling research.
  • 9/1991-6/1996 Assistant Professor
    Department of Electrical and Computer Engineering
    Oregon State University, Corvallis, OR
  • 6/1995-9/1995 Summer Visiting Faculty
    Microprocessor Product Division 6, Intel Corp., Hillsboro, OR
    Examine the P6 Micro-Architecture for possible selftimed implementation
  • 2/1985-4/1991 VLSI Systems Design Manager
    The MOSIS Service
    USC/ISI, Marina del Rey, California
    Supervised a group of seven professionals.
    Designed CAD/CAE tools interface for MOSIS users.
    Designed and Layout MOSIS' pad driver library cells
    Developed the new MOSIS' service "netlist-to-parts"
    Designed the functional test vehicle and developed its test plan for yield monitoring
  • 9/1987-12/1987 Instructor
    Department of Electrical Engineering
    USC, Los Angeles, California
    Taught a graduate level VLSI systems design course with 40 on
    campus students and 15 off-campus professionals.
  • Summer 1985 Laboratory Teaching Assistant
    National Science Foundation VLSI Summer Teacher's course
    Setup design workstation and CAD software.
    Answered questions on tools and CMOS design.
  • 6/1984-9/1984 Research Intern
    IBM T.J. Watson Center
    Yorktown Hts., New York
    Participated in the Logic Synthesis Project. Wrote codes in PL/C
    to perform gate-level logic minimization.
  • 12/80-12/83 Research Assistant
    Department of Computer Science
    UCLA, Los Angeles, California
    Research on the application of functional programming language for real-time simulation.
    Project supported by NASA Lewis Research Center.
  • 6/80-9/80 Junior Consultant
    A. D. Little Inc.
    San Francisco, California
    Development of microprocessor based consumer products.


    AWARDS:

  • 1996 OSU College of Engineering Electrical and Computer Engineering Engelbrecht Award
  • 1995 OSU College of Engineering Carter Award for Outstanding and Inspirational Teaching


    PROFESSIONAL ACTIVITIES:

  • Technical Program Chair of IEEE Mesa Workshop on Computer Elements, 2001
  • Committee member
    Technical Committee member of IEEE ASIC Conference, 1992-2000
    Technical Committee member of IEEE ASIC Conference, 1992-2000
    Organizing Committee member of IEEE ASIC Conference, 1997
    Associate Session Technical Committee member of ISCAS, 1996
  • Referee
    IEEE Transactions on VLSI Systems,
    IEEE Transactions on Computers,
    IEEE Journal of Solid-State Circuits,
    IEEE Transactions on Circuits and Systems II,
    IEEE Transactions on Education, Journal of Computer and Software Engineering,
    International Journal of Microwave and Millimeter Wave-CAE,
  • Book Reviewer
    Book on Re-Configurable Hardware
    Book on Digital Design Using FPGA
    Book on Microprocessor Systems Design
  • Professional Society Membership
    IEEE and Computer Society
    Eta Kappa Nu Electrical Engineering Honor Society


    PATENTS:

  • "Non-stalling Cyclic Counterflow Pipeline Microarchitecture," pending.
  • "Pulse Skewed CMOS Logic," pending.
  • "A modified least recently allocated cache replacement method and apparatus,"
  • "Method and Apparatus for Charge-transfer Pre-sensing," pending
  • "One-transistor and one-capacitor dram cell for logic process technology," pending
  • Four other pending patents


    PUBLICATIONS:

  • Book Chapter
  • S. L. Lu, "Memory Architecture," section in Encyclopedia, to appear in Feb. 1999.
  • R. Ramachandran and S. L. Lu, "Carry Logic," section in Encyclopedia, to appear in Feb. 1999.
  • S. L. Lu, "Memory Devices," section in CRC Electronics Handbook, Dec. 1996.

  • Journals
  • Panel member of a special feature article on "Higher Performance and Low Power Design,"
    IEEE Design & Test of Computers Magazine , Vol. 15, No. 3, July-Sept. 1998.
  • S. L. Lu, "Low Voltage Manchester Adder Design," IEE Electronics Letters, July 1997. pp. 1358-1359.
  • R. Ramachandran and S. L. Lu, "Efficient Arithmetic with Selftiming," IEEE
    T. on VLSI Systems. Dec. 1996, pp. 445-454
  • S. Kotikalapoodi, B. Lee, S. L Lu, and A. R. Hurson, "Architectural Support
    for Fine-grain Multithreading on Stock Processors," Int. Journal of Mini and
    Microcomputers, Vol. 15, No. 1, pp.14-19.
  • C. M. Chang and S. L. Lu, "The Design of a Static MIMD Dataflow Processor Using
    Micropipelines," IEEE Transaction on VLSI Systems, Sept. 1995.
  • S. L. Lu and Jack Kenney, "The Design of a Most-Significant-Bit-First Bit-Serial
    Multiplier," IEE Electronics Letters, July 1995.
  • S. L. Lu, "Implementation of Micropipelines in Enable/Disable CMOS Differential
    Logic," IEEE Transaction on VLSI Systems, June 1995.
  • S. L. Lu, "An Improved Design of CMOS Multiple-Input Muller-C-Elements," IEE
    Electronics Letters, August 1993.
  • S. L. Lu, "The Design of Hardware Efficient Self-Timed Circuits," IEE Electronics
    Letters, January 1993.
  • S. L. Lu and M. D. Ercegovac, "Evaluation of Two Summand Adders in CMOS Differential
    Logic," IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, August 1991, pp. 1152-1160.
  • S. L. Lu and M. D. Ercegovac, "A Novel CMOS Implementation of Double-Edge-Triggered
    Flip-Flops," IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, August 1990, pp. 1008-1010.
  • C. P. Wan, B. Sheu and S. L. Lu, "Device and Circuit Simulation Interface
    for an Integrated VLSI Design Environment," IEEE Transaction on Computer-Aided
    Design, Vol. 7, No. 9, Sept. 1988, pp. 998-1004.
  • S. L. Lu, "Implementation of Iterative Networks with Differential CMOS,"
    IEEE Journal of Solid-State Circuits, Vol. 23, No. 4, Aug. 1988, pp. 1013-1017
  • S. L. Lu, "A Safe Single Phase Clocking Scheme for CMOS," IEEE Journal of
    Solid-State Circuits, Vol. 23, No. 1, Feb. 1988, pp. 280-283.
  • G. Huang and S. L. Lu, "Some Theoretical Problems and Algorithms for Identification
    of Distributed Parameter Systems," Journal of Shandong University, China, No. 1, March 1983, pp. 10-22.

  • Conferences and Reports
  • T. Liu and S. L. Lu, "Circuit Level Speculation,"
    Proc. of 33rd ACM Microarchitecture COnference, 2000.
  • R. Larson and S. L. Lu, "Interpolation Based Frequency Synthesizer,"
    Proc. of 13th EEE International ASIC Conference, 2000.
  • K. R. Cho, R. Larson and S. L. Lu, "A New Phase Accumulator with Signle Transistor Path uing Pass Transistor Logic,"
    Proc. of 12th EEE International ASIC Conference, 1999.
  • K. Janik and S. L. Lu, " An implemenation of an Artificial Retina," iaccepted, Compcon 7, 1999.
  • M. F. Miller, K. Janik and S. L. Lu, "Non-Stalling Counterflow Microarchitecture",
    proceedings of the 4th High Performance Computer Architecture," Las Vegas, NV., Feb. 1998.
  • K. Janik, S. L. Lu and M. F. Miller, "Advances of the Counterflow Pipeline
    Microarchitecture," proceedings of the 3rd High Performance Computer Architecture
    Conference, TX, Feb. 1997.
  • Jim Li and S. L. Lu, "Low Power Design of Two-dimensional DCT," the Proceedings
    of the 8th IEEE International ASIC Conference, Sept. 1996.
  • Ken Janik and S. L. Lu, "Design of a Synchronous Counterflow Pipeline Processor,"
    Proceedings of the 1996 International Symposium on Circuits and Systems. May 1996.
  • R. Ramachandran and S. L. Lu, "An Efficient Selftimed Adder Design," Proceedings
    of the 8th IEEE International ASIC Conference, Austin, Texas, Sept. 1995 (Nominated for best papers).
  • K. Janik and S. L. Lu, "VLSI Implementation of a 32-bit Kozen Formulation Ladner/Fischer
    Parallel Prefix Adder," Proceedings of the 8th IEEE International ASIC Conference,
    Austin, Texas, Sept. 1995.
  • S. L. Lu and H. Stier, "Pipelined MSB-First Multiplier Design for FIR Filter,"
    Proceedings of 1995 International Symposium on VLSI Technology, Systems, and Applications, May 1995.
  • C. M. Chang and S. L. Lu "Transient Delay and Steady State Analysis of Micropipelines,"
    Proceedings of 1995 International Symposium on VLSI Technology, Systems, and Applications, May 1995.
  • S. L. Lu, "Experience with teaching ASIC Design Using Xilinx' FPGA and Mentor
    Tools," Proceedings of the 7th IEEE ASIC Conference, Rochester New York, Sept. 1994.
  • S. L. Lu, "Low Power Selftimed Design Using CMOS Differential Circuits,"
    Proceedings of the 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, Aug. 1994.
  • S. Langley, S. L. Lu and J. Kenney, "A System Architecture for multi-level
    decision feedback equalization," The 6th Joint MMM-Intermag Conference, Albuquerque,
    New Mexico, June 1994.
  • S. L. Lu and C. M. Chang, " Modelling of a Self-timed DataFlow Processor in
    VHDL," Proceedings of the 6th IEEE ASIC Conference, Rochester New York, Sept.. 1993.
  • C. M. Chang and S. L. Lu, "Micro Data Flow Processors," Proceedings of IEEE
    Pacific Rim Conference on Comm., Computers and Signal Processing, 1993.
  • L. Merani and S. L. Lu, "A Self-timed Approach to VLSI Digital Filter Design,"
    Proceedings of IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 1993.
  • S. L. Lu and L. Merani, "Micro DataFlow," Proceedings of the 5th IEEE ASIC
    Conference, Rochester New York, Sept.. 1992.
  • T. Wuu, J. Pi and S. L. Lu, "A Netlist Based Language for ASIC Prototyping,"
    Proceedings of 3rd IEEE ASIC Conference, Rochester New York 1990.
  • S. L. Lu, "Incremental versus Conventional ASIC Design Cycle," Proceedings
    of the 3rd IEEE ASIC Conference, Rochester New York 1990.
  • S. L. Lu, "A Single-Phase Clocked NOR/NOR CMOS Programmable Sequential Array
    Structure," ISI Research Report-89-230, April 1989.


    CONSULTATION EXPERIENCE

  • United Nation Assignment to China's Water Resources Ministry
  • CRISC - startup company in the area of MPEG chip design
  • several other companies in the area of computer application and embedded control
    RESEARCH INTERESTS:

  • Computer System Design; Embedded System Design; Computer Architecture;
  • Low Power ASIC Design; Design for Test; Computer Aided-Design Algorithms;
  • Design of Selftimed Circuits and Systems; Computer Arithmetic;
  • Hardware Description Language.


    TEACHING INTERESTS:

  • Courses currently teaching or have taught::
    Microprocessor Based System Design (ten times at the senior/graduate level);
    VLSI System Design (four times at the senior/graduate level and once at the graduate level);
    Digital Design Using Field Programmable Gate Arrays (FPGAs) (three times at the graduate level)
    Digital Design with VHDL (once at the graduate level)
    Computer Memory Systems (once at the graduate level)
    Design Automation and CAD Algorithm (once at the graduate level);
    Selftimed Circuits (once at grad);
  • Other courses of interests:
    Computer Architecture;
    Digital Circuit Design and Analysis;
    Digital Logic/System Design;
    Computer Arithmetic


    STUDENTS

    Graduated 30 MS and 2 PhD students (major advisor). Currently advising 7 MS and 3 PhD students.


    CURRENT RESEARCH GRANTS:

  • "Low Voltage Enabling Technology," Intel, 1997-2000, $109,000, PI
  • "Smart Parking Lot," Dept. of Transportation, 1998-1999, $64,000, Co-PI
  • "Intel Faculty Fellowship," Intel, 1999, $45,000, PI


    PAST GRANT:

  • "Cryogenic High-Speed Digital Filter Design," Westinghouse, 1995-1998, $230,000, PI.
  • "Intelligent Radar Reader Board," Oregon Dept. of Transportation, 1997, $49,995, Co-PI
  • "Implementation and Synthesis of Micropipelines in CMOS Differential Logic,"
    NSF, RIA, 1992-1996, $108,000, PI..
  • "Semi-Automated Technical Support for Silicon Brokerage - MOSIS," USC/ISI (ARPA),
    1992-1994, $64,378, P.I.


    CASH GIFT

    Intel Corp., $5,000, 1996


    EQUIPMENT GIFT

  • Equipment Gift, Intel, $100,000, 1995-1999
  • Free Fabrication Gift, Orbit Semiconductor, $70,000, 1992-1995
  • Parts Gift, AMD, $15,000, 1992-1994
  • Software Gift, Xilinx, $29,200, 1993
  • Equipment Gift, Tektronix, $180,000, 1993
  • Equipment Gift, HP/Apollo, $8,000, 1993
  • Parts Gift, Intel, $8,000, 1993
  • Parts Gift, Analog Devices, $1,600, 1993
  • Software Gift, Viewlogic, $360,000, 1992