ECE679 Special Topic on Computer Engineering
Welcome to FPGA Design Using VHDL course homepage!
This page provides access to class info outside of the classroom.
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Annoucements
What to turn in for your lab assignments
Visit the ModelSim Homepage to get free Eval version of the VHDL simulation tool Model Sim Technology
Visit the Examplar Homepage to get a LeonardoSpectrum Demo Exemplar
Xilinx's phone Number is 408-559-7778. Please call them or fill up an online webpage for a databook
Visit the Xilinx Homepage for many good applicaiton notes and data sheets - Xilinx
Visit the Orcad Homepage for many good applicaiton notes and data sheets - OrCad
Visit the Viewlogic Homepage for many good applicaiton notes and data sheets - Viewlogic
Visit the Mentor Graphics Homepage Mentor Graphics
Course Information
Lecture Notes
Week 1
Introduction and FPGA Design Paradimg
Introduction to VHDL
Review of Digital Design
Week 2
Review of Digital Design (Continue)
VHDL Modeling Overview
Structural Specification
Introduction to tools
Week 3
VHDL Constructs
More on tools - Leonardo Synthsis Tool
Week 4
Introduction to FPGA/CPLD Architectures
Xilinx CLB Architecture and Design Examples
Introduction to Xilinx' Implementation Tools
Week 5
More on FPGA/CPLD Architectures
VHDL Constructs (Continue)
LAB examples
Week 6
More on Dataflow Description
State Machine Specifications
Overloading
Week 7
Lab Assignment #3 Postscript File
Bresenham's circle algorithm explanation
Attributes
Behavior Description
Week 8
Synthesis
Other finer points of VHDL
Timing Methodology
Week 9
Coding Style
Using VHDL for Programmable Logic Design
GSR with logic
How to use DCI
How to use DCM
Lab3 Examples
Week 10
Design of a CPU - Par-1
VHDL codes for i8051
Original page for i8051
Other Topics
Design for Test
Week 11
Project
Lab Assignments
Other Links
UIDAHO
UIDAHO
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