VHDL Language

Purpose of this lecture:

  • Main Concepts of the Language
  • VHDL Components - Entity and Architecture
  • Timing Model

    Languages Main Concepts


    Hardware is inherently concurrent. Concurrent means activities can and will happen in parallel. That is whenever there is an event, all possible consequences of the event will happen at the same time.


    VHDL allows mixing of descriptions of blocks with different styles. This is a form of concurrency.

    Sequential Statements

    Even though hardware is concurrent, we need to have the capability to describe a design or model with sequential statements similar to the conventional procedure languages such as C or Pascal. VHDL supports sequential statements.


    This is very important for digital systems.

    OVerview of VHDL Model Components

    We have already mentioned through an example that a VHDL description requires two components - namely ENTITY and ARCHITECTURE. We say that ENTITY defines that interface of a component we are describing. And the ARCHITECTURE defines a component's functionality. From our example we see that several alternative architectures may be specified for use with the same entity. We also mentioned that there are three ways (or styles) one may use to describe the function of a component:

  • Structural
  • Dataflow (or RTL)
  • Behavioral

    We can also insert timing and delay descriptions of the component into the code.

    The fundamental unit for component behavior description is the process. Processes may be explicitly or implicitly defined. They are packaged in architectures. The primary communication mechanism is the signal.

    Besides ENTITY and ARCHITECTURE there are three other design units in VHDL. First two are CONFIGURATION and PACKAGE. CONFIGURATION is like a parts' list and PACKAGE is a collection of definitions and declarations which can be referenced by many ENTITies in a design at the same time. It is similar to the header files in C. Placing definitions shared by many entities (designs) in a common place help design teams to work more consistently. A Package may contain definitions of constant values, user defined data types, component declaration or subprograms in VHDL, for example. A PACKAGE also has a PACKAGE BODY. We will cover these three in more details later. Before we go into the details of ENTITY and ARCHITECTURE, we would like to mention one final concept of VHDL. After you have written your VHDL program, a tool is used to "compile" (or "analyze") the code. This process translate the VHDL source code into a binary representation which can be simulated. This binary file is stored in a directory on your computer. And the directory storing this file has a logical name known in VHDL as LIBRARY. All VHDL simulator and synthesizer access binary files by mapping the LOGICAL name to a directory. VHDL allows a default LIBRARY called WORK to be defined which is used to store and access files from a physical directory if no particular LIBRARY is specified.

    ENTITY Declarations

    The primary purpose of the entity is to declare the signals in the component's interface. All signals to be interfaced are listed in the PORT clause. In some respect ENTITY is similar to the SYMBOL in a schematic entry tool.

    PORT Clause

    PORT clause declares the interface signals of the object to the outside world. There are three parts to a PORT clause- Name, Mode, Data Type. There are 5 PORT modes available:

    IN --
    indicates that the only signal driver is outside this block being declared.
    OUT --
    indicates that the only signal driver is within the component.
    BUFFER --
    indicates there may be signal drivers both inside and outside of the block. However only one may drive this signal at one time
    INOUT --
    indicates there may be signal drivers both inside and outside of the block. Many may drive this signal at one time, but a bus resolution function is required to determine what values the signal will assume.
    LINKAGE --
    indicates the the location of the signal driver is not known. This only indicate a connection exists.
    GENERIC Clause

    Syntax:: GENERIC (generic_name : type [:= default_value]);

    Example:: GENERIC (MY_ID : Integer : =37);

    Architecture Description

    An entity may have several architecture descriptions associated with it. One useful application of this ability is when a design is described in different level abstraction. There may be behavior, RTL (microachitecture, netlist of gates descriptions of the same entity. They can be interchanged. As mentioned before there are three ways to describe the architecture of a entity. They are:

  • Dataflow
  • BEHAVIORAL Now let us use the example of half adder we have seen to build up a full adder.
    ENTITY fulladd IS
        PORT  (a, b, cin : IN bit;
               sum, cout : OUT bit);
    END fulladd;
    ARCHITECTURE struct of fulladd IS
        SIGNAL i1, i2, i3 : bit;
        COMPONENT hadd PORT (i1, i2 : IN BIT; o1, o2 : OUT BIT); END COMPONENT;
        u1 : hadd PORT MAP (A, B, i1, i2);
        u2 : hadd PORT MAP (i2, cin, i3, sum);
        carry <= i3 OR i1 AFTER 3 NS;
    In this example we covered two declarations within ARCHITECTURE - local signal declarations and COMPONENTs.


    Delay types

  • Transport delay
  • Inertial delay
  • Delta delay


    ENTITY timing_demo IS 
        port (ao, bo, co : OUT BIT);
    END timing_demo;
    ARCHITECTURE concurrent OF timing_demo IS
        SIGNAL a, b, c : BIT := '0';
        a <= '1' AFTER 2 NS;
        b <= NOT a AFTER 3 NS;
        c <= NOT b AFTER 4 NS;
        ao <= a;
        bo <= b;
        co <= c;
    END concurrent;

    This example generates an event (0 to 1) on AO at time 2NS and an event (0 to 1) on CO at time 4NS. There is no other events on BO.

    Convince yourself that that is true. The reason is that there is a "2NS" pulse on A from time 0NS to 2NS. This pulse is smaller than 3NS which is the implied inertial delay of B. Therefore there is no event change on BO. If you change the VHDL description to

        a <= '1' AFTER 4 NS;
        b <= NOT a AFTER 3 NS;
        c <= NOT b AFTER 4 NS;
    There will be events on B) now. Also, if the delay of NOT gate for b is 2 NS for the original VHDL code. This is exactly the same as the pulse on a (from 0 to 2ns), this pulse will be passed into B. The code will look like:
    -- Modified From the textbook Problem 4.2
    ENTITY timing_demo IS 
        port (ao, bo, co : OUT BIT);
    END timing_demo;
    ARCHITECTURE concurrent OF timing_demo IS
        SIGNAL a, b, c : BIT := '0';
        a <= '1' AFTER 2 NS;
        b <= NOT a AFTER 2 NS;
        c <= NOT b AFTER 4 NS;
        ao <= a;
        bo <= b;
        co <= c;
    END concurrent;
    This time B will have event again.

    The last delay is delta delay. It is not a "real" delay. It is necessary because hardware is concurrent while software is "sequential" inherently. Delta delay is needed to allow simulator to operate on events that happens simultaneously.