How to implement DCI on Virtex-II devices.

For example if your board uses LVTTL standard for the I/O to communicate on board. This corresponds to LVDCI_33 standard for digitally controlled impedance functionality on each FPGA. “LVDCI_33” means “Low Voltage Digitally Controlled Impedance, 3.3V”. To implement this, the following steps must be taken:

1) V_cco pins must be connected to the appropriate V_cco voltage based on the IO-standards in that bank. This is taken care of on the schematic, where all V_cco pins are connected to 3.3V.

2) Correct DCI I/O buffers must be used in the ISE software. Use “IBUF_LVDCI_33” or “OBUF_LVDCI_33” for this. I added the appropriate attributes to the primitives for these buffers. For convenience, I also made 16-bit versions (for busses), a bi-directional version, and 3-state output versions (i.e. “OBUFT…”).

3) External reference resistors must be connected to VRN and VRP pins. This is taken care of on the schematic.

4) Each bank must be treated identically with respect to voltage pins and IO-standards used. This is not an issue because we are using only one IO-standard. All voltage pins and voltage reference pins are wired correctly on the schematic.

5) Make sure that the nets between the PADs and the buffers have the correct IO-standard attribute. This may be automatic when using the DCI buffers correctly as in item two above. To set the attributes, or to double check that they are set, use syntax “NET <net name> IOSTANDARD = OBUF_LVDCI_33”, where <net name> is the name between the IPAD and IBUF or between the OPAD and OBUF (should be the same name as the port name). This attribute can be entered through the NCF or UCF file (and can probably be set right in the schematic).

So, only items two and five need to be addressed, because the rest were taken care of in hardware. There is an example on page 282 of a VHDL instantiation (as opposed to schematic instantiation), but the schematic is probably easier.

The IPADs and OPADs should be set to specific pins according to the PIN-OUTs listed in the design specification, appendix H.