Notes on DCM in Virtex-II devices.

We are using the DCM (Digital Clock Manager) ISE primitives to implement a “Frequency Synthesizer”. I modified the primitives by setting the appropriate attributes to obtain a divide by 2, divide by 3, and multiply by 4 synthesis (e.g. “DCM_DIVIDE3” primitive).

The CLK_OUT pin on the symbol is the synthesized frequency clock signal. This signal passes through a BUFGMUX so that it can drive internal logic.

To use the primitives that I have made, the CLK_IN pin must be driven by an IBUF corresponding to the FPGA’s input clock pin (as specified in the PIN-OUT list of the design specification, appendix H). style="mso-spacerun: yes"> 

If the CLK_OUT pin drives off-chip devices, the signal must pass through an OBUF (not BUFG) before passing out through the specified pin (according to design specification, appendix H).

The RESET pin is active high and is asynchronous. It should only be asserted when reconfiguring the FPGA or when changing the input frequency. Hold the line high for 2ns.