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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:09:18 01/26/2009 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Adder4 is
    Port ( x : in  STD_LOGIC_VECTOR(3 downto 0);
           y : in  STD_LOGIC_VECTOR(3 downto 0);
           ci : in STD_LOGIC;
			  co : out STD_LOGIC;
			  s : out STD_LOGIC_VECTOR(3 downto 0));
end Adder4;


architecture Structure of Adder4 is
component FullAdder
				port (a : in STD_LOGIC;
						b : in STD_LOGIC;
						cin : in STD_LOGIC;
						cout : out STD_LOGIC;
						sum : out STD_LOGIC);
end component;

signal c_int: STD_LOGIC_VECTOR(3 downto 1); --internal signal

begin   --instantioate four copies of the FullAdder
 
FA0: FullAdder 
port map(a => x(0), b => y(0), cin => ci, cout => c_int(1), sum => s(0));
 
FA1: FullAdder 
port map(a => x(1), b => y(1), cin => c_int(1), cout => c_int(2), sum => s(1));

FA2: FullAdder 
port map(a => x(2), b => y(2), cin => c_int(2), cout => c_int(3), sum => s(2));

FA3: FullAdder 
port map(a => x(3), b => y(3), cin => c_int(3), cout => co, sum => s(3));

end Structure;