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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:25:50 01/30/2009 
-- Design Name: 
-- Module Name:    traffic - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity traffic is
    Port ( s : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  clk : in STD_LOGIC;
           g1 : out  STD_LOGIC;
           y1 : out  STD_LOGIC;
           r1 : out  STD_LOGIC;
           g2 : out  STD_LOGIC;
           y2 : out  STD_LOGIC;
           r2 : out  STD_LOGIC);
end traffic;

architecture Behavioral of traffic is

type statetype is	(reset_st, y1_st, r1_st, timer_st, y2_st);
signal current_state, next_state: statetype;
	
signal counter : std_logic_vector(3 downto 0):= "0000";
signal timer_reset : std_logic;
signal timer_en : std_logic;


begin

statereg: process(clk)
		begin
			if (clk='1' and clk'event) then
				if (reset='1') then -- intial state
					current_state <= reset_st;
				else
					current_state <= next_state;
				end if;
			end if;
		end process;
		
comblogic: process (current_state, s, counter)
		begin
		--default outputs
		g1<= '0';
		y1<= '0';
		r1<= '0';
		g2<= '0';
		y2<= '0';
		r2<= '0';
		timer_reset <= '0';
		timer_en <= '0';
			
			case current_state is
				when reset_st =>
					g1 <= '1'; --  green 1 on
					r2 <= '1'; --  red 2 on
					if (s = '0') then
						next_state <= reset_st;
					else
						next_state <= y1_st;
					end if;
				when y1_st =>
					y1 <= '1'; -- yellow 1 on
					r2 <= '1'; -- red 2 stays on
					next_state <= r1_st;
				when r1_st =>
					r1 <= '1'; -- red 1 on
					r2 <= '1'; -- red 2 stays on
					timer_reset <= '1';
					next_state <= timer_st;
				when timer_st =>
					r1 <= '1'; -- red 1 on
					g2 <= '1'; --green 2 on
					timer_en <= '1';
					if counter = "1111" then
						next_state <= y2_st;
					else
						next_state <= timer_st;
					end if;
				when y2_st =>
					r1 <= '1';
					y2 <= '1';
					next_state <= reset_st;
					
			end case;
		end process;

--Counter process		
timer1:	process (clk) 
			begin
				if clk ='1' and clk'event then
					if timer_reset ='1' then 
						counter <= (others => '0');
					elsif  timer_en ='1' then
						counter <= counter + 1;
					end if;
				end if;
			end process;

end Behavioral;