When and Where:
MWF 11:00-11:50 am; KEC 1003
Instructor:
Roger Traylor
Office: 3095 Kelley Engineering Center
E-mail: traylor@ece.NOSPAM.edu (replace "NOSPAM" with "orst")
Office Hours: Tu 3:30 - 5:00pm, Wed 3:00-4:00pm or by appointment
TA:
TBA
E-mail: TBA@ece.SPAM.edu (replace "SPAM" with "orst")
Office: TBA
Office Hours: TBA
Text:(not manditory)
Essential VHDL
RTL Synthesis Done Right
By Sundar Rajan
(self-published)
Class Objective:
At the completion of this class, each student should be able to:
You may work in groups on homework and projects if you wish. Sharing of design approaches, philosophy, block diagrams or coding ideas is strongly suggested. However, sharing of detailed information such as state machine diagrams, or actual VHDL code is not approved and will meet with the strongest action that I can bring.
A mail reflector (or group, list) for the class will be established by the beginning of class. This "mail group" is where you find information about important "stuff". The mailgroup is how I communicate with you outside the classroom. It can also be used as an interactive forum where you discuss problems and solutions. Such usage is encouraged.
Students who register early for ECE474/574 are automatically added to the class mail list. You will be added to the list later if you register late. If auditing, I will have to manually add you to the list. In either case, you should be added to the list within a day or so.
The name of the class list for ECE474/574 is: ece474-w07@engr.NOSPAM.edu This name is case sensitive. You know what to put in place of "NOSPAM"
1) Using only the course text book, you complete a homework set.
References: None
2) You work with a group to complete a homework set.
References: I worked concurrently with Joe Smith, and Sam Brown on this
homework set as part of a study group.
3) You are stuck on how to draw a timing diagram on a homework set
and ask Joe Blow how he approached the problem.
References: Joe Blow explained how to set up the timing diagram
on problem 1.
4) You cannot get your simulation to give correct results. You look
at Sally's working code.
References: I looked at Sally's code to try and figure out what
was going wrong.
Week | Date | Subject | Design Work | Supplemental Reading |
|---|---|---|---|---|
| 1 | 1/7, 1/9, 1/11 |
ASIC Design Basics -Top-down and Bottom-up -A hybrid Top-down Strategy? -Practical limitations -Architecture and Paritioning Design Stage Progression -Modeling in the Design Process Drawing Block Diagrams -Block diagrams An Intel Design Scenario Intro to HDL Design VHDL: what is it? -origins, motivation Weekly project discussion |
Exercises with Hierarchy and Design HW 1: Blocks and Gates Due Mon, Jan 14, in ECE office by 5pm tas.vhd fifo.vhd TAS Requirements Document(.pdf) |
Rajan: Chapt 1,2 Rajan: Chapt 9 (Design Partitioning) Rajan: Chapt 11, pgs 222-225 (Generics in Scalable and Parameterizable Design) Cramming more components onto ICs (The original paper on Moore's Law written in 1965) Good Designers Must Fail (more risk, more learning) Truthful Schedules? (Lies, damn lies, and engineering schedules) Hierarchical Design (Pros and Myths about hierarchical design) |
| 2 | 1/14, 1/16, 1/18 |
Scripting for EDA tools What makes up a script? Shells -sh, tcsh, bash Scripting languages: -PERL, TCL Testbenches Design Management Weekly project discussion Quiz 1 |
HW 2: Scripts and Testbenches Due Wed, Jan 23, to TEACH website by 11:30pm HW2 Tarball Submitting help |
Writing Shell Scripts Bash Programming Introduction Advanced Bash Programming Beginners Introductionto Perl Perl FAQ Scripting for IC Flows |
| 3 | 1/21(off), 1/23, 1/25 |
ENTITY, ARCHITECTURE, PORT -the basics of VHDL Compenent Instantiation -structural design, lables, -positional and named association GENERIC Clause Text I/O Data Types and Operators Data types Package std_logic_1164 Operators, overloading Signal Assignment Signal Assignment Busses Concurrency Conditional Signal Assignment incomplete specifications Selected Signal Assignment use of OTHERS making choices with "|" Weekly project discussion |
HW 3: Combo VHDL circuits .synopsys_dc.setup Due Fri, Feb 1, in ECE Office site by 5:00pm |
Rajan: Chapt 14, pgs 291-303 (text i/o) |
| 4 | 1/28, 1/30, 2/1 |
PROCESS statement Sequential operators and Variables IF and relational operators CASE statement and OTHERS LOOP statement Delays in VHDL Attributes Synthesis Intro TCL for DC Partitioning for Synthesis Weekly project discussion |
HW 4: Synthesis scripting with Combo Logic Synthesis boilerplate Due Wed, Feb 6, to TEACH web site by 11:30pm |
Rajan: Chapt 3, (gates, decoders, encoders) Rajan: Chapt 11, (loops, attributes, varaibles, generate) Rajan: Chapt 3, pgs 141-155 (delay types, ) |
| 5 | 2/4, 2/6, 2/8 |
Inferring Storage Elements State Machines in VHDL -Coding syles -Enumerated States -Glitchless State Machines Mealy Outputs Sync vs Async Reset Inclass Exercise - What am I? Weekly project discussion |
HW 5: State element synthesis Waveforms for HW5 Due Wed, Feb 13, in class |
Rajan: Chapt 5 (Registers and Latches) Synchronous vs Asynchronous Resets (Which type of reset should I use?) X's in Digital Simulation (When "X" is your friend) Rajan: Chapt 6 (Finite State Machines) Opencores coding guidelines Coding guidelines (lite) |
| 6 | 2/11, 2/13, 2/15 |
Interactive Classwork Session -TAS data paths -TAS state machines Midterm (inclass) |
HW 6: HDL State Machines Due Wed, Feb 20, in class Simulation dofiles: TBD dofiles in tarball golden_results |
|
| 7 | 2/18, 2/20, 2/22 |
Timing and area constraints Timing Constraints Problems and Questions -Latches -Combinatorial loops -Failure to run at speed -SDF errors Debugging Pointers Timing Verification -Static and Dynamic -Multicycle paths -False paths Static Timing/ Reports Weekly project discussion |
HW 7: Sequential Logic Synthesis Full submittal Due Wed, Feb 27, to TEACH web site by midnight list dofile Skeleton synthesis script | |
| 8 | 2/25, 2/27, 2/29 |
Metastability Design for Test -Fault test vs. verification -Finding and propagating faults -Ad hoc, partial scan, full scan -Test vectors -DFT-aware design Partial Scan Iddq Testing Problems caused by DFT Fixing Hold Violations Weekly project discussion |
HW 8: scan insertion Due Wed, Mar 5, in class or my office by 5pm, electronic part by midnight implement_scan script schematic - noscan schematic - scan ready |
Scan ATPG process guide |
| 9 | 3/3, 3/5, 3/7 |
Equivalency Checking - part 1 Equivalency Checking - part 2 Discussion of Final Project |
Final Project: 16x16 multiplier Due Mon, Mar 17, to TEACH web site by midnight multiplier_spec.pdf testbench Hennessy and Patterson multiplier block diagram for multiplier |
Functional Verification |
| 10 | 3/10, 3/12, 3/15 |
(3/10)Discussion of Final Project (3/12)Eric Campbell - Mentor Graphics Topics: -achieving timing during synthesis -testbench evolution, force files to transactions (3/15)Class eval/recap -Snacks provided |
Questions, suggestions?.... Mail to:
traylor@ece.SPAM.edu (replace SPAM with orst)
