Overview

Formal verification is of crucial significance in the development of hardware and software systems. In the last decade, tremendous progress was made in both the speed and capacity of constraint technology. Most notably, Boolean Satisfiability (SAT) solvers have become orders of magnitude faster and capable of handling problems that are orders of magnitude bigger, thus enabling the formal verification of more complex computer systems. As a result, the formal verification of hardware and software has become a promising area for research and industrial applications. Constraints have applications to all formal verification methods. Particularly, the efficient use of constraints can make or break a formal verification run, and can result in orders of magnitude speedup and orders of magnitude increase in scalability for solving of larger problems.

The main goal of the Constraints in Formal Verification workshop is to bring together researchers from the CSP/SAT/SMT and the formal verification communities, to describe new applications of constraint technology to formal verification, to disseminate new challenging problem instances, and to propose new dedicated algorithms for hard formal verification problems. This workshop will be of interest to researchers from both academia and industry, working on constraints or on formal verification and interested in the application of constraints to formal verification.

Scope

The scope of the workshop includes topics related to the application of constraint technology to formal verification, namely:

• application of constraint solvers to hardware verification;
• application of constraint solvers to software verification;
• dedicated solvers for formal verification problems;
• challenging formal verification problems.

Location

The workshop will take place in the Doubletree Hotel in Austin Texas, on November 5, 2015. It will be structured to allow ample time for discussion and demonstration of new tools and new problem instances.

Submissions

Submissions should be in the IEEE style and in one of the following types:

• a regular paper of up to 6 pages;
• a short paper of up to 4 pages, describing an industrial experience.

Papers should be submitted via EasyChair.

Important Dates

The important dates for the workshop are as follows (EXTENDED):

Invited Speakers

Santosh Nagarakatte, Rutgers University, New Brunswick, U.S.A.
Talk title: Lightweight Formal Methods for LLVM Verification

Corina Pasareanu, Carnegie Mellon/NASA Ames Research Center, U.S.A.
Talk title: On the Probabilistic Analysis of Software

General Chair

Miroslav Velev, Aries Design Automation, U.S.A.
Email: mvelev@gmail.com

Program Chair

Alex Groce, Oregon State University, U.S.A.
Email: agroce@gmail.com

Publicity Chair

Kristin Yvonne Rozier, University of Cincinnati, U.S.A.
Email: rozierky@ucmail.uc.edu

Program Committee