CS472: Computer Architecture

Course Description

• Functional organization of digital Computer architecture using processors, memories, and I/O devices as building blocks. Issues involved in the design of instruction set architecture, processor, pipelining and memory organization. Design philosophies and trade-offs involved in Reduced Instruction Set Computer (RISC) architectures. PREREQ: ECE 375. CROSSLISTED as ECE 472.

Instructor: Bruce D'Ambrosio, 107 Dearborn, 737 5563, dambrosi@cs.orst.edu
office hours: mon 2-3, fri 2-3
TA:

• Madhusudhanan madhusan@cs.orst.edu tues 2-4 115 Dearborn
• Maithily Mundle mundle@cs.orst.edu weds 2-4 115 Dearborn

Grading:

• Written Homework: weekly, 30%
• Midterm: 30% each
• Final: 40%

Homework

• Due 4/7 in class: 2.1-2.6, 2.10-2.13, 2.18-21
• Due 4/16: 3.2, 3.4, 3,5, 3.6, 3.9, 3.19, 3.20 + optional:
  find out the ISA-level code generated on a machine of your choice from the C-level switch statement discussed on pg 129 of the text.
• Due 4/23: 4.2, 4.4, 4.10, 4.11, 4.16, 4.23, 4.28, 4.44, 4.45, 4.46
• Due 5/7: 5.1, 5.2, 5.5, 5.7, 5.22, 5.26, 5.27
• Due 5/14: 6.2, 6.3, 6.4, 6.7, 6.30, 6.33
• Due 5/28: 7.1-7.7, 7.10, 7.12, 7.20, 7.33
• EXTRA CREDIT, DUE 6/9: 7.48
  This is worth one regular homework assignment

Syllabus

• Week 1: review of ISA, performance evaluation (Chapters 1-2)
• Week 2: Chapter 3
• Week 3: Chapters 3-4
• Week 4: Chapters 4-5
• Week 5: Chapters 5
• Week 6: Chapters 5-6
• Week 7: Chapters 6-7
• Week 8: Chapter 7
• Week 9: Chapter 8
• Week 10: Chapter 9

Class Materials

Grades So Far: here