IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems

January 2005 -- Special Issue on Design Automation and Test in Europe 2004

• Andrei Radulescu, John Dielissen, Kees Goossens, Santiago Gonzalez Pestana, Om Prakash Gangwal, Edwin Rijpkema, and Paul Wielage, An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. (1638)
• Pietro Babighian, Luca Benini, Enrico Macii, A Scalable Algorithm for RTL Insertion of Gated Clocks based on Observability Don't Cares Computation. (1707)
• S. Padmanaban and S. Tragoudas, Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams. (1620)
• A.Paschalis, D.Gizopoulos, Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors. (1655)
• Kihwan Choi, Ramakrishna Soma, Massoud Pedram, Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-off based on the Ratio of Off-chip Access to On-chip Computation Times. (1681)
• Joel R. Phillips, L. Miguel Silveira, Poor Man's TBR: A Simple Model Reduction Scheme. (1618)
• Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stephane Donnay, Georges G.E. Gielen, and Hugo J. De Man, Digital ground bounce reduction by supply current shaping and clock frequency modulation. (1652)
• Zhe Wang, Rajeev Murgai and Jaijeet Roychowdhury, ADAMIN: Automated, Accurate Macromodelling of Digital Aggressors for Power and Ground Supply Noise Prediction. (1728)

Short Papers:
• Ch. Grimm, W. Heupke, and K. Waldschmidt, Analysis of Mixed-Signal Systems with Affine Arithmetic. (1617)
• Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha, Threshold Network Synthesis and Optimization and its Application to Nanotechnologies. (1657)
• A. La Rosa, L. Lavagno, C. Passerone, Implementation of a UMTS Turbo-decoder on a dynamically reconfigurable platform. (1673)

February 2005

• Marcus T Schmitz, Bashir M Al-Hashimi, Petru Eles, Co-Synthesis of Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution. (1208)
• Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu, A Method for Reducing the Target Fault List of Crosstalk Faults in Synchronous Sequential Circuits. (1359)
• Le Cai and Yung-Hsiang Lu, Energy Management Using Buffer Memory for Streaming Data. (1472)
• Peng Li and Lawrence T. Pileggi, Compact Reduced-Order Modeling of Weakly Nonlinear Analog and RF Circuits. (1370)
• Guoqing Chen and Eby G. Friedman, An RLC Interconnect Model Based on Fourier Analysis. (1480)
• Hyeong-Ju Kang and In-Cheol Park, SAT-Based Unbounded Symbolic Model Checking. (1536)
• F. Pecheux, C. Lallement, A. Vachoux, VHDL-AMS and Verilog-AMS as Alternative Hardware Description Languages for Efficient Modeling of Multi-Discipline Systems. (1446)
• Jiang Brandon Liu and Andreas Veneris, Incremental Fault Diagnosis. (1514)
• Ting Mei, Jaijeet Roychowdhury, Todd S. Coffey, Scott A. Hutchinson, David M. Day, Robust, Stable Time-Domain Methods for Solving MPDEs of Fast/Slow Systems. (1546)

Short Papers:
• Yoonseo Choi and Taewhan Kim, Memory Layout Techniques for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design. (1420)
• Irith Pomeranz and Sudhakar M. Reddy, On Masking of Redundant Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. (1350)
• Chirayu S. Amin, Masud H. Chowdhury, and Yehea I. Ismail, Realizable Reduction of Interconnect Circuits Including Self and Mutual Inductances. (1530)
• Ahmad Al-Yamani, Subhasish Mitra, and Edward J. McCluskey, Optimized Reseeding by Seed Ordering and Encoding. (1578)
• A.P.Vinod, E.M-K.Lai, and A.B.Premkumar, On The Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpressions. (1386)

March 2005

• Victor Bourenkov, Kevin G. McCarthy, Alan Mathewson, MOS Table Models for Circuit Simulation. (1529)
• Krishnendu Chakrabarty, Vikram Iyengar and Mark D. Krasniewski, Test Planning for Modular Testing of Hierarchical SOCs. (1579)
• Sheldon X.-D. Tan, A General Hierarchical Circuit Modeling and Simulation Algorithm. (1651)
• Pongstorn Maidee, Cristinel Ababei, Kia Bazargan, Timing-driven Partitioning-based Placement for Island Style FPGAs. (1422)
• Saibal Mukhopadhyay, Arijit Raychowdhury, and Kaushik Roy, Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry. (1527)
• Donald Chai and Andreas Kuehlmann, A Fast Pseudo-Boolean Constraint Solver. (1569)
• M.Psarakis, D.Gizopoulos, A.Paschalis, Built-In Sequential Fault Self-Testing of Array Multipliers. (1604)
• Satish Pillai and Margarida F. Jacome, Predicated Switching - Optimizing Speculation on EPIC Machines. (1384)
• Jason Cong, Jie Fang, Min Xie and Yan Zhang, MARS - A Multilevel Full-Chip Gridless Routing System. (1512)
• Kai Wang, and Malgorzata Marek-Sadowska, On-chip Power-Supply Network Optimization using Multigrid-based Technique. (1601)
• Lin Zhong and Niraj K. Jha, Interconnect-aware Low Power High-level Synthesis. (1254)

Short Papers:
• Maged Ghoneima, Yehea Ismail, Optimum Positioning of Interleaved Repeaters in Bidirection Buses. (1360)
• Spyros Tragoudas and Vijay Nagarandal, On-Chip Embedding Mechansisms for Large Sets of Vectors for DelayTesting. (1479)
• Suvodeep Gupta and Srinivas Katkoori, Intra-Bus Crosstalk Estimation Using Word-Level Statistics. (1533)
• Payam Heydari and Massoud Pedram, Capacitive Coupling Noise in High-Speed VLSI Circuits. (1677)

April 2005

• Anand Ramachandran and Margarida F. Jacome, Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing. (1356)
• R.B. Reese, M.A. Thornton, C. Traver, D. Hemmendinger, Early Evaluation for Performance Enhancement in Phased Logic. (1414)
• Hung-Ming Chen, Li-Da Huang, I-Min Liu, and D.F. Wong, Simultaneous Power Supply Planning and Noise Avoidance in Floorplan Design. (1428)
• Jianwen Zhu, Silvian Calman, Context-Sensitive Symbolic Pointer Analysi. (1554)
• Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion Mandoiu, Qinke Wang and Bo Yao, The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. (1394)
• Bikram Baidya and Tamal Mukherjee, Layout Verification for Mixed-domain Integrated MEMS. (1417)
• Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C.K.Cheng, Jun Gu, Buffer Planning as an Integral Part of Floorplanning with Consideration of Routing Congestion. (1587)
• R. I. Bahar, H. Y. Song, K. Nepal, J. Grodstein, Symbolic Failure Analysis of Complex CMOS Circuits due to Excessive Leakage Current and Charge Sharing. (1388)
• Jingcao Hu and Radu Marculescu, Energy- and Performance-Aware Mapping for Regular NoC Architectures. (1505)
• Sampath Dechu, Zion Cien Shen and Chris C. N. Chu, An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and Obstacle Considerations. (1559)
• Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy, Finite Memory Test Response Compactors for Embedded Test Applications. (1743)

Short Papers:
• Chenggang Xu, Terri Fiez and Karti Mayaram, On the Numerical Stability of Green's Function for Substrate Coupling in Integrated Circuits. (1679)
• Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh, On Effective Slack Management in Post-Scheduling Phase. (1515)
• Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, A Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip. (1416)

May 2005 -- Special Issue on International Symposium on Physical Design 2004

• Mario R. Casu and Luca Macchiarulo, Throughput-Driven Floorplanning with Wire Pipelining. (1860)
• Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar, Early-stage Power Grid Analysis for Uncertain Working Modes. (1837)
• Jaskirat Singh, Sachin S. Sapatnekar, Congestion-aware Topology Optimization of Structured Power/Ground Networks. (1654)
• Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, and Xinning Wang, A Predictive Distributed Congestion Metric With Application To Technology Mapping. (1859)
• Haoxing Ren, David Z. Pan, David S. Kung, Sensitivity Guided Net Weighting for Placement Driven Synthesis. (1865)
• Natarajan Viswanathan and Chris Chong-Nuen Chu, FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model. (1923)
• Andrew B. Kahng and Qinke Wang, Implementation and Extensibility of an Analytic Placer. (1927)
• A. R. Agnihotri, S. Ono, C. Li, M. C. Yildiz, A. Khatkhate, C.-K. Koh, P. H. Madden, Mixed Block Placement via Fractional Cut Recursive Bisection. (1838)
• Qinghua Liu, Malgorzata Marek-Sadowska, A Study of Netlist Structure and Placement Efficiency. (2046)
• Kai Wang, Yajun Ran, Hailin Jiang, and Malgorzata Marek-Sadowska, General Skew Constrained Clock Network Sizing based on Sequential Linear Programming. (1921)
• Rafael Escovar, Salvador Ortiz, Roberto Suaya, An Improved Long Distance Treatment for Mutual Inductance. (1862)

June 2005

• Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects. (1418)
• Dong Xiang, Ming-Jing Chen, Jia-guang Sun: Hideo Fujiwara, Improving Test Effectiveness of Scan-Based BIST by Scan Chain Partitioning. (1574)
• Weiping Shi and Zhuo Li, A Fast Algorithm for Optimal Buffer Insertion. (1675)
• Mohammad Gh. Mohammad and Kewal K. Saluja, Optimizing Program Disturb Fault Tests Using Defect-based Testing. (1706)
• Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling. (1800)
• D. Maslov, G. W. Dueck, and D. M. Miller, Toffoli Network Synthesis with Templates. (1528)
• Bertozzi Davide, Benini Luca, De Micheli Giovanni, Error control schemes for on-chip communication links: the energy-reliability trade-off. (1590)
• S. Hamdioui and J.D. Reyes, New Data-Background Sequences and Their Industrial Evaluation for Word-Oriented Random-Access Memories. (1701)
• Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, and D. T. Lee, Crosstalk- and Performance-Driven Multilevel Full-Chip Routing. (1477)
• Kyu-Il Lee, Chanho Lee, Hyungsoon Shin, Young June Park, and Hong Shick Min, Efficient Frequency-domain Simulation Technique for Short Channel MOSFET. (1649)

Short Papers:
• Jun Chen, Lei He, Piece-wise linear model for transmission line with capacitive loading and ramp input. (1624)
• Yong Chang Kim, Vishwani D. Agrawal, and Kewal K. Saluja, Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits. (1724)
• Dan Zhao and Shambhu Upadhyaya, Dynamically Partitioned Test Scheduling with Adaptive TAM Configuration for Power-constrained SoC Testing. (1684)
• A. Kabbani, D. Al-khalili, and A. J. Al-khalili, Delay Analysis of CMOS Gates Using Modified Logical Effort Model. (1715)

July 2005

• Le Yan, Jiong Luo and Niraj K. Jha, Joint Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. (1552)
• Kavel M. Buyuksahin and Farid N. Najm, Early Power Estimation for VLSI Circuits. (1734)
• Biplab K Sikdar, Niloy Ganguly, and P Pal Chaudhuri, Fault Diagnosis of VLSI Circuits with Cellular Automata based Pattern Classifier. (1795)
• Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma, Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. (1823)
• Amit Chowdhary and John P. Hayes, Area-optimal Technology Mapping for Field-Programmable Gate Arrays. (1410)
• Xun Liu and Marios C. Papaefthymiou, HyPE: Hybrid Power Estimation for IP-Based Systems-on-Chip. (1786)
• Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang, Spanning Graph Based Non-Rectilinear Steiner Tree Algorithms. (1818)
• Shankar Balachandaran and Dinesh Bhatia, A-Priori Wirelength and Interconnect Estimation Based on Circuit Characteristics. (1396)
• Nahri Moreano, Edson Borin, Cid de Souza, and Guido Araujo, Efficient Datapath Merging for Partially Reconfigurable Architectures. (1759)
• Weiping Liao and Lei He and Kevin Lepak, Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level. (1890)
• Dongwoo Lee, David Blaauw, Dennis Sylvester, Static Leakage Reduction through Simultaneous Vt/Tox and State Assignment. (1669)
• Zhenhai Zhu, Ben Song and Jacob K. White, Algorithms in FastImp: A Fast and Wideband Impedance Extraction Program For Complicated 3-D Geometries. (1588)

Short Papers:
• Fatih Kocan and Mehmet H. Gunes, On the ZBDD-based Nonenumerative Path Delay Fault Coverage Calculation. (1924)
• M. Moiz Khan, Spyros Tragoudas, Rewiring for Watermarking Digital Circuit Netlists. (1815)

August 2005

• Bo Hu , Malgorzata Marek-Sadowska, Multi-level Fixed-points Addition Based VLSI Placement. (1777)
• Xiaochun Duan, Kartikeya Mayaram, An Efficient and Robust Method for Ring Oscillator Simulation Using the Harmonic Balance Method. (1918)
• Koji Ara and Kei Suzuki, Fine-Grained Transaction-Level Verification: Using a Variable Transactor for Improved Coverage at the Signal Level. (1876)
• Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail, Weibull Based Analytical Waveform Model. (1873)
• Darko Kirovski, Milenko Drinic, and Miodrag Potkonjak, Engineering Change Protocols for Behavioral and System Synthesis. (1349)
• Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, and Yuhong Zheng, Compressible Area Fill Synthesis. (1658)
• Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar, Power Grid Analysis using Random Walks. (1919)

Short Papers:
• Bing Zhong, Tao Hu, Dawei Fu, Steven L. Dvorak, and John L. Prince, A Study of a Hybrid Phase-Pole Macromodel for Transient Simulation of Complex Interconnects Structures. (1611)
• Hiren D. Patel, Sandeep K. Shukla, Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models. (2039)
• Hao Yu and Lei He, A Provably Passive and Cost Efficient Model for Inductive Interconnects. (1804)
• Irith Pomeranz and Sudhakar M. Reddy, On Fault Equivalence, Fault Dominance and Incompletely Specified Test Sets. (1917)
• Jun Chen, Lei He, Worst-Case Crosstalk Noise for Non-Switching Victims in High-speed Buses. (1627)
• Sheldon X.-D. Tan, Weikun Guo, Zheyu Qi, Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits. (1913)
• Xiaoming Yu, Miron Abramovici, Elizabeth M. Rudnick, Sequential Circuit ATPG Using Combinational Algorithms. (1723)

September 2005 -- Special Section on International Syposium on Quality Electronic Design 2004

Special Section Papers:
• Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski, Delay Fault Diagnosis Using Timing Information. (1952)
• Valeriy Sukharev, Physically-Based Simulation of Electromigration Induced Failures in Copper Dual damascene Interconnects. (1962)
• Medha Kulkarni, Tom Chen, A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. (1991)
• Jianwen Zhu, Fang Fang, Qianying Tang, A New Layout Migration Engine for Hard Intellectual Property Libraries. (1901)
• Man L Mui, Kaustav Banerjee and Amit Mehrotra, Supply and Power Optimization in Leakage Dominant Technologies. (2296)

Short Papers:
• Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng, Application Specific Worst Case Corners using Response Surfaces and Statistical Models. (1986)

Regular Issue Papers:
• Young-Su Kwon and Chong-Min Kyung, Performance-Driven Event-Based Synchronization for Multi-FPGA Simulation Accelerator with Event Time-Multiplexing Bus. (1774)
• Hao Gang Wang, Chi Hou Chan, Leung Tsang, A New Multi-Level Green’s Function Interpolation Method for Large Scale Low Frequency EM Simulations. (1900)
• Dhiraj K. Pradhan, Chunsheng Liu, EBIST: A Novel Test Generator with Built-In Fault Detection Capability. (1808)
• Shu Yan, Vivek Sarin, and Weiping Shi, Sparse Transformations and Preconditioners for 3-D Capacitance Extraction. (1929)
• Carl-John H. Seger, Robert B. Jones, John W. O'Leary, Tom Melham, Mark D. Aagaard, Clark Barrett, Don Syme, An Industrially Effective Environment for Formal Hardware Verification. (1693)
• Hongliang Chang and Sachin S. Sapatnekar, Statistical Timing Analysis Under Spatial Correlations. (1979)
• Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe and Malgorzata Marek-Sadowska, Eliminating False Positives in Crosstalk Noise Analysis. (1783)

October 2005

• Tatjana Pesic, Nebojsa Jankovic, A Compact Non-Quasi-Static MOSFET Model based on the Equivalent Non-Linear Transmission Line. (1946)
• Clemens Heitzinger, Alireza Sheikholeslami, Jong Mun Park, Siegfried Selberherr, A Method for Generating Structurally Aligned Grids for Semiconductor Device Simulation. (1708)
• Ken Eguro and Scott Hauck, Resource Allocation for Coarse-Grain FPGA Development. (1687)
• Yongsang Cho, Irith Pomeranz, and Sudhakar M. Reddy, On Reducing Test Application Time for Scan Circuits Using Limited Scan Operations and Transfer Sequences. (1922)
• Rong Jiang, Wenyin Fu, Charlie Chung-Ping Chen, EPEEC: Comprehensive SPICE-Compatible Reluctance Extraction for High-Speed Interconnects above Lossy Multilayer Substrate. (2068)
• Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe, Quasi-static scheduling of independent tasks for reactive systems. (1513)
• Ruediger Ebendt, Wolfgang Guenther and Rolf Drechsler, Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization. (1756)
• Soumitra Bose, Amit Nandi, Schematic Array Models for Associative and Non-Associative Memory Circuits. (1852)
• Alexander Smith, Andreas Veneris, Moayad Fahim Ali, Anastasios Viglas, Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. (1844)
• Dongkun Shin and Jihong Kim, Intra-Task Voltage Scheduling on DVS-Enabled Hard Real-Time Systems. (1537)

Short Papers:
• H. Saaied, D. Al-Khalili, A.J. Al-Khalili and M. Nekili, Simultaneous Adaptive Wire Adjustment and Local Topology Modification for Tuning a Bounded Skew Clock Tree. (1621)
• Gethin Norman, David Parker, Marta Kwiatkowska, Sandeep Shukla, Evaluating the Reliability of NAND Multiplexing with PRISM. (1980)
• Hsu-Wei Huang, Cheng-Yeh Wang, and Jing-Yang Jou, An Efficient Heterogeneous-Tree Multiplexer Synthesis Technique. (2005)

November 2005

• James Chien-Mo Li, Edward J. McCluskey, Diagnosis of Resistive and Stuck-open Defects in Digital CMOS ICs. (1910)
• Bo Yang, Ramesh Karri and David A. McGrew, Divide-and-Concatenate: An Architecture Level Optimization Technique for Universal Hash Functions. (2085)
• Mehdi Baradaran Tahoori, Subhasish Mitra, Application-Independent Testing of FPGA Interconnects. (1892)
• H-G. D. Stratigopoulos and Y. Makris, Non-Linear Decision Boundaries for Testing Analog Circuits. (1998)
• Sarvesh Bhardwaj, Sarma Vrudhula and David Blaauw, Probability Distribution of Signal Arrival Times using Bayesian Networks. (1915)
• Ken Tseng and Mark Horowitz, False Coupling Exploration in Timing Analysis. (2089)
• Chao Huang, Srivaths Ravi, Anand Raghunathan and Niraj. K. Jha, Generation of Distributed Logic-Memory Architectures through High-Level Synthesis. (1636)
• Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj.K.Jha, Input Space Adaptive Optimization for Embedded Software Synthesis. (1828)
• Fei Li and Lei He, Power Modeling and Characteristics of Field Programmable Gate Arrays. (2071)
• Federico Angiolini, Luca Benini, Alberto Caprara, An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning. (1714)
• D. Pamunuwa, S. Elassaad, H. Tenhunen, Modeling Delay and Noise in Arbitrarily-Coupled RC Trees. (1933)
• Shinobu Nagayama, Tsutomu Sasao, On the Optimization of Heterogeneous MDDs. (2014)

December 2005

• Gang Qu, Analysis of Energy Reduction on Dynamic Voltage Scaling-Enabled Systems. (2011)
• Lihong Feng, Evgenii B. Rudnyi and Jan G. Korvink, Preserving the film coefficient as a parameter in the compact thermal model for fast electro-thermal simulation. (2172)
• Mehdi B. Tahoori, Jing Huang, Mariam Momenzadeh and Fabrizio Lombardi, Characterization, Test and Logic Synthesis of And-Or-Inv (AOI) Gate Design for QCA Implementation. (2143)
• Joon-Ho Lee and Qing H. Liu, An Efficient 3-D Spectral Element Method for Schrodinger Equation in Nanodevice Simulation. (2219)
• Saibal Mukhopadhyay, Hamid Mahmoodi, and Kaushik Roy, Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nano-Scaled CMOS. (2045)
• Qiang Xu and Nicola Nicolici, Modular SOC Testing with Reduced Wrapper Count. (2076)
• Ivan Auge, Frederic Petrot, Francois Donnet and Pascal Gomez, Platform based design from parallel C specifications. (2030)

Short Papers:
• Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi, Longest Path Selection for Delay Test under Process Variation. (2093)
• A.P.Vinod and E.M-K.Lai, An Efficient Coefficient-Partitioning Algorithm for Realizing Low Complexity Digital Filters. (2032)
• Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng, Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing for Two-Pin Nets. (2069)
• Sandip Kundu, Sujit T Zachariah, Yi-Shing Chang, Chandra Tirumurti, On Modeling Crosstalk faults. (2156)
• Patrick Schaumont, David Hwang, Ingrid Verbauwhede, Platform-based design for an embedded fingerprint authentication device. (2146)