Paper Review References

    Integrated accelerometers (Tetsuya Kajita)
     
  1. N. Yazdi, F. Ayaze, and K. Najafi, "Micromachined inertial sensors," Proc. of IEEE, vol. 86, No. 8, Aug. 1998.
  2. M. Lemkin, M. Ortiz, N. Wongkomet, B. Boser, and J. Smith, "A 3-axis surface micromachined delta-sigma accelerometer," ISSCC Digest of Technical Papers, pp.202-203, Feb. 1997.
  3. T. Smith, O. Nys, M. Chevroulet, Y. DeCoulon, and M. Degrauwe, "A 15-b electromechanical sigma-delta converter for acceleration measurements," ISSCC Digest of Technical Papers, pp.160-161, Feb. 1994.
  4. C. Lu, M. Lemkin, and B. Boser, "A monolithic surface micromachined accelerometer with digital output," ISSCC Digest of Technical Papers, pp.160-161, Feb. 1995.
  5. C. Lu, M. Lemkin, and B. Boser, "A monolithic surface micromachined accelerometer with digital output," IEEE J. Solid-State Circuits, vol. 30, pp.1367-1373, Dec. 1995.
  6. P. Ferguson and G. Temes, "The application of switched-capacitor and delta-sigma technologies to a micro-machined accelerometer," CDADIC report, Jun. 1995.
  7. W. Henrion, L. DiSanza, M. Ip, S. Terry, and H. Jerman, "Wide dynamic range direct digital accelerometer," 1990 Solid-State Sensor and Actuator Workshop, SC, June 1990, Technical Digest, IEEE, pp.153-157, 1990.

    Low-voltage switched-capacitor circuits (Mustafa Keskin)
     
  1. E. Bidari et al., "Low-voltage switched-capacitor circuits", 1999 ISCAS.
  2. V. Peluso et al., "A 900 mW 40 uW switched-opamp delta-sigma modulator with 77 dB dynamic range," 1998 ISSCC Digest, pp. 68-69.
  3. T. Kawahara et al., "Internal voltage generator for low voltage quarter- micrometer flah memories," JSSC, January 1998, pp. 126-132.
  4. A. Baschirotto and R. Catello, "A 1-V 1.8 MHz CMOS swithed-opamp SC filter with rail-to-rail output swing," JSSC, Dec. 1997, pp. 1979-1986.
  5. M. Steyaert et al., " Custom analog power design: the problem of low voltage and mismatch," IEEE-CICC, 1997, pp. 285-292.
  6. J-I Wu et al., "1.2 V CMOS switched capacitor circuits," IEEE-ISSC, Feb. 1996, pp. 388-389.
  7. K. Sawada, "An on-chip high voltage generator circuit for EEPROM's with a power supply voltage below 2V," Symp. VLSI circuits Dig. Tech. Papers, June 1995, pp. 75-76.
  8. J. Crols and M. Steyaert, "Switched opamp: an approach to realize full CMOS circuits at very low supply voltages," JSSC, Aug. 1994, pp. 936-942.
  9. Y. Nakagome et al., "An Experimental 1.5 V 64-Mb DRAM," JSSC, April 1991, pp. 465-472.
  10. R. Castello and L. Tomasini, "1.5 V high performance SC filters in BICMOS technology," JSSC, July 1991, pp. 930-936.
  11. F. Maleborti, "Reduction of 1/f noise in SC ladder filters using correlated double sampling method," Proc. IEEE-ICCS, Beijing, 1985, pp. 108-11.
  12. J.F. Dickson, " On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique," JSSC, June 1976, pp. 374-387.

    Phase noise in oscillators (Kunal Godbole)
     
  1. Ali Hajimiri and Thomas Lee, "A general theory of phase noise in electrical oscillators," IEEE Journal of Solid-State Circuits, Vol 33, No. 2, February 1998.
  2. Behzad Razavi, "A study of phase noise in CMOS oscillators," IEEE Journal of Solid-State Circuits, Vol 31, No. 3, March 1996.
  3. A. A. Abidi and R.G. Meyer, "Noise in relaxation oscillators," IEEE Journal of Solid-State Circuits, Vol SC-18, No. 6 , December 1983.

    Bandgap circuits (Prasad Divekar)
     
  1. B. Song and P. Gray, "A precession curvature-compensated CMOS bandgap reference", IEEE J. of Solid-State Circuits, Vol. SC-18, no. 6, pp. 634-643, December 1991.
  2. P. Gray and R. G. Meyer, "Analog integrated circuits", 3rd. Ed., John Wiley & Sons, New York, 1993.
  3. D. A. Johns and K. Martin, "Analog integrated circuit design", 1st. Ed., John Wiley & Sons, New York, 1997.

    Acquisition time of phase-locked loops (Ryan Perigny)
     
  1. Hurng-Liangh, Jinn-Chang Wu, "Fast response phase detector for a phase-locked loop", International Journal of Electronics, vol. 78, pp. 557-562, 1995.
  2. P. Larsson, "Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector", IEE Proceedings - Communications, vol. 142, pp. 221-226, Aug. 1995.
  3. Mark Van Paemel, "Analysis of a charge-pump PLL: A new model", IEEE Transactions on Communications, vol. 42, pp. 2490-2498, July 1994.
  4. F.M. Gardner, "Charge-pump phase-lock loops", IEEE Transactions on Communications, vol. 28, pp. 1849-1858, Nov. 1980.
  5. David Johns, Ken Martin, Analog Integrated Circuit Design, New York: John Wiley & Sons, Inc., 1997.

    Threshold voltage fluctuations (Crystal Maddix)
     
  1. T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's," IEEE Trans. Electron Devices, vol. 41, p. 2216, 1994.
  2. E. Takeda, G. Jones, and H. Ahmed, "Constraints on the application of 0.5-um MOSFET's to ULSI systems," IEEE Trans. Electron Devices, vol. ED-32, p. 322, 1985.
  3. Y. Okumura, M. Shirahata, A. Hachisuka, T. Okudaira, H. Arima, and T. Matsukawa, "Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability," IEEE Trans. Electron Devices, vol. 39, p. 2541, 1992.
  4. H. Kurata and T. Sugii, "Self-aligned control of threshold voltages in sub-0.2-um MOSFETs," IEEE Trans. Electron Devices, vol. 45, p.2161, 1998.

    Charge Pumps (Abdurrahman Unsal)
     
  1. Jieh Tsomg Wu, "MOS charge pumps for low-voltage operation", IEEE J. Solid-State Circuits, Vol. 33,pp. 592-597 April 1998.
  2. Frank Goodenough, "Charge pumps covert power efficiently without inductors", Electronic Design, pp. 189-194, November 3, 1997.
  3. Piere Favrat, "A high-efficiency CMOS voltage doubler", IEEE J. Solid-State Circuits, Vol. 33, pp. 410-417, March 1998.
  4. Jieh Tsomg "1.2V CMOS switched-capacitor circuits", 1996 IEEE International Solid-State Circuits Conference, pp 388-389.

    Charge pump PLL -- design and application (Lei Wu)
     
  1. I.Novof et "Fully integrated CMOS PLL with 15 to 240 MHz locking range and +/- 50 psec jitter" ISSCC Dig.Tech. Papers, Feb 1995.
  2. I.A Young et "A PLL generator with 5 to 110MHz of lock range for microprocessors," IEEE JSSC, Nov 1992.
  3. L.De Vito " A versatile clock recovery architecture and monolithic implementation," from book: monolithic PLL and clock recovery circuits by Behzad Razavi, 1996.
  4. F.M. Gardner, "Charge pump phase lock loops," IEEE Tran. Comm., Nov 1980.

    Low-voltage CMOS operational amplifier design (Dingming Xie)
     
  1. G. Palmisano et al, "A 1.5-v high drive capability CMOS op-amp," IEEE J. Solid-State Circuits, vol.34, pp. 248-252, February 1999.
  2. B. Hosticka et al, "Low-voltage CMOS analog circuits," IEEE Trans. Circuits Syst. I, vol. 42, pp. 864-871, Nov. 1995.
  3. A. Coban et al, "Low voltage analog IC design in CMOS technology," IEEE Trans. Circuits Syst. I, vol. 42, pp. 955-958, Nov. 1995.
  4. G. Palmisano and G. Palumbo, "A very efficient CMOS low voltage output stage," Electron. Lett., vol. 31, no. 21, pp. 1830-1831, 1995.
  5. J. Huijsing and D. Linebarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE J. Solid-State Circuits, vol. SC-20, pp. 1144-1150, Dec. 1985.

    A Nyquist Rate Delta-Sigma A/D Converter (Iron Zhang)
     
  1. E.T.King, A. Eshraghi, Ian Galton and T.S. Fiez, "A Nyquist-rate delta-sigma A/D converter," IEEE J. of Solid State Circuits, Vol. 33, No. 1, Jan. 1998.
  2. Other references listed at the end of this paper.

    Segmented noise-shaped scrambling DAC (Shengting Huang)
     
  1. R. Adams, K.Q. Nguyen, K. Sweetland, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling", IEEE J. Solid State Circuits, vol. 33, pp. 1871-1878, Dec 1998

    Low-noise low-drift transducer ADC (Mark Cheng)
     
  1. D. McCartney and A. Sherry, "A low-noise low-drift transducer ADC," IEEE Journal of Solid State Circuits, Vol. 32. No. 7, July 1997.
  2. D. A. Kerth and D. S. Piasecki, "An over sampling convert for strain gauge transducers," IEEE J. Solid-State Circuits, Vol. 27, pp. 1689-1696.
  3. D. McCartey and D. R. Welland, "Delta sigma modulator having programmable gain/attenuation," U.S. patent 5134 401, July 1992.

    Determination of stability using return ratios (Jose Silva)
     
  1. P. Hurst and S. Lewis, "Determination of stability using return ratios in balanced fully differential circuits", IEEE Transactions on Circuits and Systems, vol. 42, pp. 805-817, December 1995.
  2. D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, New York, 1997.
  3. R. Gregorian and G. Temes, Analog MOS Integrated Circuits for Signal Processing, Wiley, New York, 1986.
  4. Personal communication with Tetsuya Kajita, OSU, February 1999.

    Delta-sigma PLL (John Zhang)
     
  1. Ian Galton, William Huff, Paolo Carbone, and Eric Siragusa, "A delta-sigma PLL for 14-b, 50k samples frequency-to-digital conversion of a 10 MHz FM signal", IEEE journal of Solid-State Circuits, Vol. 33 No. 12, Dec. 1998.
  2. Benoft R. Veilettw and Gorgon W. Robarts, "On-chip measurement of jitter transfer function of charge-pump PLL", IEEE Journal of Solid-State Circuits, Vol. 33 No. 3, Mar. 1998.
  3. D.M.W. Leenaerts, G.G. Persoon, and B.M. Putter, "CMOS switched current PLL", IEEE Proc. Circuits Devices Syst., Vol. 144 No. 2, April 1997.
  4. I.Galton, "Analog-input digital PLLs for precise frequency and phase demodulation", IEEE Trans. Circuits Syst.--II, Vol 42, Oct. 1995.

    SOI process--scaling and design considerations (Babu Nepali)
     
  1. Jean-Pierre Colinge, "Silicon-On-Insulator technology: materials to VLSI", 1991.
  2. Shojiro Asai and Yasuo Wada, "Technology challenges for integration near and below 0.1 um", Proc. IEEE, Vol. 85, No. 4, April 1997.
  3. D. Davari, R. Dennard, and G. Shahidi, "CMOS scaling for high performance and low power -- the next ten years", Proc. IEEE, vol. 83, pp. 595-606, April 1995.
  4. W.G. Kang, J.S. Kang, K. Lee, "Grounded Body SOI (GBSOI) N-MOSFET by wafer bonding", IEEE Elec. Device Letters, vol.16, No. 1, Jan, 1995.
  5. T. Fuse, Y. Oowaki, & Collogues, "0.5V SOI CMOS pass-gate logic", IEEE Intl. Solid-State Circuits Conference, 1996.
  6. IEEE SOS/SOI Technology Conference, Oct, 1990.
  7. Jan M. Rabaey, "Digital integrated circuits", Prentice Hall Electronics and VLSI series, 1996.

    Active-feedback CMOS cascode current mirror (Junlin Zhou)
     
  1. Ali Zeki and Hakan Kuntman, "Accurate active-feedback CMOS cascode current mirror with improved output swing", Internation Journal of Electronics, 1998, Vol. 84, No.4, 335-343.
  2. Ali Zeki and Hakan Kuntman, H., 1995, "New MOSFET model suitable for analog IC Analysis", International Journal of Electronics, 78, 247-260.
  3. Yang, H.C., and Allstot, D.J., 1990, "An active feedback cascode current source", IEEE Transations on Circuits and Systems, 37, 644-646.
  4. Sackinger, E., and Guggenbuhl, W., 1990, "A high-swing, high impedance MOS cascode circuit", IEEE Journal of Solid-state Circuits, 25,289-298.
  5. Palmisano, G., Palumbo, G., and Pennisi, S., 1995, "High linearity CMOS output stage", IEEE Electronics Letters, 31, 789-790.

ECE-626 / EECS / moon@oregonstate.edu