//-------------------------------------------------------------------
// counter for inclass exercise 
//-------------------------------------------------------------------
//
//This code implements a 32-bit counter.  Signal reset_n is asynchronous 
//active low and forces count_out to 0x00.
//

module counter (
       input             clk,       // input clock
       input             reset_n,   // reset async active low
       input             enable,    // counter enable
       output reg [31:0] count_out  // counter output
       );

 always_ff @ (posedge clk, negedge reset_n) 
   if(!reset_n)       count_out <= '0 ;           //reset to zero
   else if (enable)   count_out <= count_out + 1; // count up

endmodule