#ynopsys synthesis script

#boilerplate
set hdlin_auto_save_templates true
set hdlin_check_no_latch      true

read_sverilog  counter.sv
#read_sverilog  jhsn_cntr.sv

current_design counter 
link

##### constraints are below #####

#erase all attributes and constrains from the current design
reset_design

#set_operating_conditions -max TYPICAL
set_operating_conditions -max WORST   
#set_operating_conditions -max BEST    

#set wire loading model to 8000
set_wire_load_model -name 8000

#set wire loading mode to top  
set_wire_load_mode top

# Define the clock period and clock port (10ns clock period)
create_clock -period 7.5  -name my_clock  [get_ports clk]

# Set the clock uncertainty to +/- 20pS
set_clock_uncertainty -setup .020 [get_clocks my_clock]
set_clock_uncertainty -hold  .020 [get_clocks my_clock]

#---- input constraints ----
# set the "input valid" delay to 5.0nS
set_input_delay  7.0 -max -clock my_clock [remove_from_collection [all_inputs] [get_clocks my_clock ]]

#set the fastest input data arrival time to check for hold time changes to 100pS
set_input_delay -min 0.150 -clock my_clock [remove_from_collection [all_inputs] [get_clocks my_clock ]]

# Indicate the drive characteristics of what drives the inputs:
set_driving_cell -lib_cell SDFFARX1  [remove_from_collection [all_inputs] [get_clocks my_clock]]


#---- output constraints ----
# set the setup time requirements for the next block to 5nS
set_output_delay 5.0 -max -clock my_clock [all_outputs]

# set the hold time requirements for the next block to 150pS
set_output_delay -min -0.150  -clock my_clock [all_outputs]

# Indicate the capacitive loading on the outputs equal to 5 inv_2 inverter inputs
set_load [expr 5 * [load_of saed90nm_typ/AND2X1/IN1]] [all_outputs]


compile -ungroup_all

# Make sure we are at the top level
set current_design  counter

# Generate area and constraints reports on the optimized design
report_area    > area.rpt

# Generate timing report for worst case path
report_timing  > delay.rpt

# Generate timing report for hold time 
report_timing -delay min  > hold_error.rpt 

# Save the optimized design
write -format verilog -hierarchy -output  counter.gate.v
write_sdf counter.gate.sdf -context verilog
quit