Flow report for lab1 Thu Mar 31 11:16:20 2016 Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow Summary 3. Flow Settings 4. Flow Non-Default Global Settings 5. Flow Elapsed Time 6. Flow OS Summary 7. Flow Log 8. Flow Messages 9. Flow Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ ; Flow Status ; Successful - Thu Mar 31 11:16:20 2016 ; ; Quartus Prime Version ; 15.1.1 Build 189 12/02/2015 SJ Lite Edition ; ; Revision Name ; lab1 ; ; Top-level Entity Name ; lab1 ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; ; Total logic elements ; 7 / 22,320 ( < 1 % ) ; ; Total combinational functions ; 7 / 22,320 ( < 1 % ) ; ; Dedicated logic registers ; 0 / 22,320 ( 0 % ) ; ; Total registers ; 0 ; ; Total pins ; 15 / 154 ( 10 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 / 608,256 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+---------------------------------------------+ +-----------------------------------------+ ; Flow Settings ; +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ ; Start date & time ; 03/31/2016 11:15:34 ; ; Main task ; Compilation ; ; Revision Name ; lab1 ; +-------------------+---------------------+ +----------------------------------------------------------------------------------------------------------------------+ ; Flow Non-Default Global Settings ; +-------------------------------------+---------------------------------+---------------+-------------+----------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+---------------------------------+---------------+-------------+----------------+ ; COMPILER_SIGNATURE_ID ; 52242604730.145944813403795 ; -- ; -- ; -- ; ; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (SystemVerilog) ; ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +-------------------------------------+---------------------------------+---------------+-------------+----------------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 1096 MB ; 00:00:19 ; ; Fitter ; 00:00:07 ; 1.0 ; 1322 MB ; 00:00:06 ; ; Assembler ; 00:00:01 ; 1.0 ; 1009 MB ; 00:00:01 ; ; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 1036 MB ; 00:00:01 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 1254 MB ; 00:00:01 ; ; Total ; 00:00:22 ; -- ; -- ; 00:00:28 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------------------------------------------------------------------------+ ; Flow OS Summary ; +---------------------------+------------------+----------------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +---------------------------+------------------+----------------+------------+----------------+ ; Analysis & Synthesis ; roger-ubuntu ; Ubuntu 14.04.4 ; 14 ; x86_64 ; ; Fitter ; roger-ubuntu ; Ubuntu 14.04.4 ; 14 ; x86_64 ; ; Assembler ; roger-ubuntu ; Ubuntu 14.04.4 ; 14 ; x86_64 ; ; TimeQuest Timing Analyzer ; roger-ubuntu ; Ubuntu 14.04.4 ; 14 ; x86_64 ; ; EDA Netlist Writer ; roger-ubuntu ; Ubuntu 14.04.4 ; 14 ; x86_64 ; +---------------------------+------------------+----------------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off lab1 -c lab1 quartus_fit --read_settings_files=off --write_settings_files=off lab1 -c lab1 quartus_asm --read_settings_files=off --write_settings_files=off lab1 -c lab1 quartus_sta lab1 -c lab1 quartus_eda --read_settings_files=off --write_settings_files=off lab1 -c lab1