// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition"

// DATE "03/31/2016 11:16:19"

// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim-Altera (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module lab1 (
	bcd_in,
	seven_seg_out,
	leds);
input 	[3:0] bcd_in;
output 	[7:1] seven_seg_out;
output 	[3:0] leds;

// Design Ports Information
// seven_seg_out[1]	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// seven_seg_out[2]	=>  Location: PIN_D1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// seven_seg_out[3]	=>  Location: PIN_G2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// seven_seg_out[4]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// seven_seg_out[5]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// seven_seg_out[6]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// seven_seg_out[7]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
// leds[0]	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
// leds[1]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// leds[2]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// leds[3]	=>  Location: PIN_A11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// bcd_in[0]	=>  Location: PIN_M1,	 I/O Standard: 2.5 V,	 Current Strength: Default
// bcd_in[1]	=>  Location: PIN_T8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// bcd_in[2]	=>  Location: PIN_B9,	 I/O Standard: 2.5 V,	 Current Strength: Default
// bcd_in[3]	=>  Location: PIN_M15,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("lab1_v.sdo");
// synopsys translate_on

wire \seven_seg_out[1]~output_o ;
wire \seven_seg_out[2]~output_o ;
wire \seven_seg_out[3]~output_o ;
wire \seven_seg_out[4]~output_o ;
wire \seven_seg_out[5]~output_o ;
wire \seven_seg_out[6]~output_o ;
wire \seven_seg_out[7]~output_o ;
wire \leds[0]~output_o ;
wire \leds[1]~output_o ;
wire \leds[2]~output_o ;
wire \leds[3]~output_o ;
wire \bcd_in[2]~input_o ;
wire \bcd_in[0]~input_o ;
wire \bcd_in[1]~input_o ;
wire \bcd_in[3]~input_o ;
wire \WideOr7~0_combout ;
wire \WideOr5~0_combout ;
wire \WideOr3~0_combout ;
wire \WideOr2~0_combout ;
wire \Decoder1~0_combout ;
wire \seven_seg_out~0_combout ;
wire \seven_seg_out~1_combout ;


// Location: IOOBUF_X0_Y23_N23
cycloneive_io_obuf \seven_seg_out[1]~output (
	.i(!\WideOr7~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[1]~output .bus_hold = "false";
defparam \seven_seg_out[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y25_N9
cycloneive_io_obuf \seven_seg_out[2]~output (
	.i(\WideOr5~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[2]~output .bus_hold = "false";
defparam \seven_seg_out[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y23_N16
cycloneive_io_obuf \seven_seg_out[3]~output (
	.i(\WideOr3~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[3]~output .bus_hold = "false";
defparam \seven_seg_out[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y23_N2
cycloneive_io_obuf \seven_seg_out[4]~output (
	.i(\WideOr2~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[4]~output .bus_hold = "false";
defparam \seven_seg_out[4]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y24_N23
cycloneive_io_obuf \seven_seg_out[5]~output (
	.i(\Decoder1~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[5]~output .bus_hold = "false";
defparam \seven_seg_out[5]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y28_N9
cycloneive_io_obuf \seven_seg_out[6]~output (
	.i(\seven_seg_out~0_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[6]~output .bus_hold = "false";
defparam \seven_seg_out[6]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y24_N16
cycloneive_io_obuf \seven_seg_out[7]~output (
	.i(\seven_seg_out~1_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\seven_seg_out[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \seven_seg_out[7]~output .bus_hold = "false";
defparam \seven_seg_out[7]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X38_Y34_N16
cycloneive_io_obuf \leds[0]~output (
	.i(!\bcd_in[0]~input_o ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\leds[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \leds[0]~output .bus_hold = "false";
defparam \leds[0]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X49_Y34_N2
cycloneive_io_obuf \leds[1]~output (
	.i(!\bcd_in[1]~input_o ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\leds[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \leds[1]~output .bus_hold = "false";
defparam \leds[1]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X49_Y34_N9
cycloneive_io_obuf \leds[2]~output (
	.i(!\bcd_in[2]~input_o ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\leds[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \leds[2]~output .bus_hold = "false";
defparam \leds[2]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X40_Y34_N2
cycloneive_io_obuf \leds[3]~output (
	.i(!\bcd_in[3]~input_o ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\leds[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \leds[3]~output .bus_hold = "false";
defparam \leds[3]~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X25_Y34_N8
cycloneive_io_ibuf \bcd_in[2]~input (
	.i(bcd_in[2]),
	.ibar(gnd),
	.o(\bcd_in[2]~input_o ));
// synopsys translate_off
defparam \bcd_in[2]~input .bus_hold = "false";
defparam \bcd_in[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y16_N22
cycloneive_io_ibuf \bcd_in[0]~input (
	.i(bcd_in[0]),
	.ibar(gnd),
	.o(\bcd_in[0]~input_o ));
// synopsys translate_off
defparam \bcd_in[0]~input .bus_hold = "false";
defparam \bcd_in[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X27_Y0_N15
cycloneive_io_ibuf \bcd_in[1]~input (
	.i(bcd_in[1]),
	.ibar(gnd),
	.o(\bcd_in[1]~input_o ));
// synopsys translate_off
defparam \bcd_in[1]~input .bus_hold = "false";
defparam \bcd_in[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X53_Y17_N15
cycloneive_io_ibuf \bcd_in[3]~input (
	.i(bcd_in[3]),
	.ibar(gnd),
	.o(\bcd_in[3]~input_o ));
// synopsys translate_off
defparam \bcd_in[3]~input .bus_hold = "false";
defparam \bcd_in[3]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N24
cycloneive_lcell_comb \WideOr7~0 (
// Equation(s):
// \WideOr7~0_combout  = (\bcd_in[3]~input_o ) # ((\bcd_in[2]~input_o  & ((!\bcd_in[1]~input_o ) # (!\bcd_in[0]~input_o ))) # (!\bcd_in[2]~input_o  & ((\bcd_in[1]~input_o ))))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(\bcd_in[3]~input_o ),
	.cin(gnd),
	.combout(\WideOr7~0_combout ),
	.cout());
// synopsys translate_off
defparam \WideOr7~0 .lut_mask = 16'hFF7A;
defparam \WideOr7~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N26
cycloneive_lcell_comb \WideOr5~0 (
// Equation(s):
// \WideOr5~0_combout  = (!\bcd_in[3]~input_o  & ((\bcd_in[2]~input_o  & (\bcd_in[0]~input_o  & \bcd_in[1]~input_o )) # (!\bcd_in[2]~input_o  & ((\bcd_in[0]~input_o ) # (\bcd_in[1]~input_o )))))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(\bcd_in[3]~input_o ),
	.cin(gnd),
	.combout(\WideOr5~0_combout ),
	.cout());
// synopsys translate_off
defparam \WideOr5~0 .lut_mask = 16'h00D4;
defparam \WideOr5~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N20
cycloneive_lcell_comb \WideOr3~0 (
// Equation(s):
// \WideOr3~0_combout  = (\bcd_in[0]~input_o ) # ((\bcd_in[2]~input_o  & !\bcd_in[1]~input_o ))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(gnd),
	.cin(gnd),
	.combout(\WideOr3~0_combout ),
	.cout());
// synopsys translate_off
defparam \WideOr3~0 .lut_mask = 16'hCECE;
defparam \WideOr3~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N30
cycloneive_lcell_comb \WideOr2~0 (
// Equation(s):
// \WideOr2~0_combout  = (!\bcd_in[3]~input_o  & ((\bcd_in[2]~input_o  & (\bcd_in[0]~input_o  $ (!\bcd_in[1]~input_o ))) # (!\bcd_in[2]~input_o  & (\bcd_in[0]~input_o  & !\bcd_in[1]~input_o ))))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(\bcd_in[3]~input_o ),
	.cin(gnd),
	.combout(\WideOr2~0_combout ),
	.cout());
// synopsys translate_off
defparam \WideOr2~0 .lut_mask = 16'h0086;
defparam \WideOr2~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N16
cycloneive_lcell_comb \Decoder1~0 (
// Equation(s):
// \Decoder1~0_combout  = (!\bcd_in[2]~input_o  & (!\bcd_in[0]~input_o  & \bcd_in[1]~input_o ))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(gnd),
	.cin(gnd),
	.combout(\Decoder1~0_combout ),
	.cout());
// synopsys translate_off
defparam \Decoder1~0 .lut_mask = 16'h1010;
defparam \Decoder1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N10
cycloneive_lcell_comb \seven_seg_out~0 (
// Equation(s):
// \seven_seg_out~0_combout  = (\bcd_in[2]~input_o  & (\bcd_in[0]~input_o  $ (\bcd_in[1]~input_o )))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(gnd),
	.cin(gnd),
	.combout(\seven_seg_out~0_combout ),
	.cout());
// synopsys translate_off
defparam \seven_seg_out~0 .lut_mask = 16'h2828;
defparam \seven_seg_out~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X1_Y24_N12
cycloneive_lcell_comb \seven_seg_out~1 (
// Equation(s):
// \seven_seg_out~1_combout  = (!\bcd_in[1]~input_o  & (!\bcd_in[3]~input_o  & (\bcd_in[2]~input_o  $ (\bcd_in[0]~input_o ))))

	.dataa(\bcd_in[2]~input_o ),
	.datab(\bcd_in[0]~input_o ),
	.datac(\bcd_in[1]~input_o ),
	.datad(\bcd_in[3]~input_o ),
	.cin(gnd),
	.combout(\seven_seg_out~1_combout ),
	.cout());
// synopsys translate_off
defparam \seven_seg_out~1 .lut_mask = 16'h0006;
defparam \seven_seg_out~1 .sum_lutc_input = "datac";
// synopsys translate_on

assign seven_seg_out[1] = \seven_seg_out[1]~output_o ;

assign seven_seg_out[2] = \seven_seg_out[2]~output_o ;

assign seven_seg_out[3] = \seven_seg_out[3]~output_o ;

assign seven_seg_out[4] = \seven_seg_out[4]~output_o ;

assign seven_seg_out[5] = \seven_seg_out[5]~output_o ;

assign seven_seg_out[6] = \seven_seg_out[6]~output_o ;

assign seven_seg_out[7] = \seven_seg_out[7]~output_o ;

assign leds[0] = \leds[0]~output_o ;

assign leds[1] = \leds[1]~output_o ;

assign leds[2] = \leds[2]~output_o ;

assign leds[3] = \leds[3]~output_o ;

endmodule