Analysis & Synthesis report for lab3
Fri Apr 29 15:20:36 2016
Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Parameter Settings for User Entity Instance: lab3pll:lab3pll_0|altpll:altpll_component
 11. altpll Parameter Settings by Entity Instance
 12. Port Connectivity Checks: "bcd_updn:bcd_updn_d2"
 13. Port Connectivity Checks: "bcd_updn:bcd_updn_d0"
 14. Post-Synthesis Netlist Statistics for Top Partition
 15. Elapsed Time Per Partition
 16. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
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agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Apr 29 15:20:36 2016       ;
; Quartus Prime Version              ; 15.1.1 Build 189 12/02/2015 SJ Lite Edition ;
; Revision Name                      ; lab3                                        ;
; Top-level Entity Name              ; lab3                                        ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 98                                          ;
;     Total combinational functions  ; 84                                          ;
;     Dedicated logic registers      ; 51                                          ;
; Total registers                    ; 51                                          ;
; Total pins                         ; 19                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22F17C6       ;                    ;
; Top-level entity name                                                      ; lab3               ; lab3               ;
; Family name                                                                ; Cyclone IV E       ; Cyclone V          ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                     ; Library ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------+---------+
; lab3.sv                          ; yes             ; User SystemVerilog HDL File  ; /home/traylor/fpga/lab3/lab3.sv                                                  ;         ;
; debouncer.sv                     ; yes             ; User SystemVerilog HDL File  ; /home/traylor/fpga/lab3/debouncer.sv                                             ;         ;
; quad_decode.sv                   ; yes             ; User SystemVerilog HDL File  ; /home/traylor/fpga/lab3/quad_decode.sv                                           ;         ;
; bcd2_7seg.sv                     ; yes             ; User SystemVerilog HDL File  ; /home/traylor/fpga/lab3/bcd2_7seg.sv                                             ;         ;
; bcd_updn.sv                      ; yes             ; User SystemVerilog HDL File  ; /home/traylor/fpga/lab3/bcd_updn.sv                                              ;         ;
; pll/lab3pll.v                    ; yes             ; User Wizard-Generated File   ; /home/traylor/fpga/lab3/pll/lab3pll.v                                            ;         ;
; altpll.tdf                       ; yes             ; Megafunction                 ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf        ;         ;
; aglobal151.inc                   ; yes             ; Megafunction                 ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/aglobal151.inc    ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                 ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratix_pll.inc   ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                 ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratixii_pll.inc ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                 ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/cycloneii_pll.inc ;         ;
; db/lab3pll_altpll.v              ; yes             ; Auto-Generated Megafunction  ; /home/traylor/fpga/lab3/db/lab3pll_altpll.v                                      ;         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Estimated Total logic elements              ; 98            ;
;                                             ;               ;
; Total combinational functions               ; 84            ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 29            ;
;     -- 3 input functions                    ; 23            ;
;     -- <=2 input functions                  ; 32            ;
;                                             ;               ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 68            ;
;     -- arithmetic mode                      ; 16            ;
;                                             ;               ;
; Total registers                             ; 51            ;
;     -- Dedicated logic registers            ; 51            ;
;     -- I/O registers                        ; 0             ;
;                                             ;               ;
; I/O pins                                    ; 19            ;
;                                             ;               ;
; Embedded Multiplier 9-bit elements          ; 0             ;
;                                             ;               ;
; Total PLLs                                  ; 1             ;
;     -- PLLs                                 ; 1             ;
;                                             ;               ;
; Maximum fan-out node                        ; reset_n~input ;
; Maximum fan-out                             ; 52            ;
; Total fan-out                               ; 476           ;
; Average fan-out                             ; 2.74          ;
+---------------------------------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                 ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node               ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                           ; Library Name ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------+--------------+
; |lab3                                    ; 84 (43)           ; 51 (22)      ; 0           ; 0            ; 0       ; 0         ; 19   ; 0            ; |lab3                                                                         ; work         ;
;    |bcd2_7seg:bcd2_7seg_0|               ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|bcd2_7seg:bcd2_7seg_0                                                   ; work         ;
;    |bcd_updn:bcd_updn_d0|                ; 8 (8)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|bcd_updn:bcd_updn_d0                                                    ; work         ;
;    |bcd_updn:bcd_updn_d1|                ; 6 (6)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|bcd_updn:bcd_updn_d1                                                    ; work         ;
;    |bcd_updn:bcd_updn_d2|                ; 10 (10)           ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|bcd_updn:bcd_updn_d2                                                    ; work         ;
;    |debouncer:debounce_enc_a|            ; 2 (2)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|debouncer:debounce_enc_a                                                ; work         ;
;    |debouncer:debounce_enc_b|            ; 2 (2)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|debouncer:debounce_enc_b                                                ; work         ;
;    |debouncer:debounce_sw|               ; 2 (2)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|debouncer:debounce_sw                                                   ; work         ;
;    |lab3pll:lab3pll_0|                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|lab3pll:lab3pll_0                                                       ; work         ;
;       |altpll:altpll_component|          ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|lab3pll:lab3pll_0|altpll:altpll_component                               ; work         ;
;          |lab3pll_altpll:auto_generated| ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|lab3pll:lab3pll_0|altpll:altpll_component|lab3pll_altpll:auto_generated ; work         ;
;    |quad_decode:quad_decode_0|           ; 4 (4)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab3|quad_decode:quad_decode_0                                               ; work         ;
+------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 51    ;
; Number of registers using Synchronous Clear  ; 9     ;
; Number of registers using Synchronous Load   ; 9     ;
; Number of registers using Asynchronous Clear ; 51    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |lab3|Selector0            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lab3pll:lab3pll_0|altpll:altpll_component ;
+-------------------------------+---------------------------+----------------------------+
; Parameter Name                ; Value                     ; Type                       ;
+-------------------------------+---------------------------+----------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                    ;
; PLL_TYPE                      ; AUTO                      ; Untyped                    ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=lab3pll ; Untyped                    ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                    ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                    ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                    ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                    ;
; INCLK0_INPUT_FREQUENCY        ; 20000                     ; Signed Integer             ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                    ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                    ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                    ;
; LOCK_HIGH                     ; 1                         ; Untyped                    ;
; LOCK_LOW                      ; 1                         ; Untyped                    ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                    ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                    ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                    ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                    ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                    ;
; SKIP_VCO                      ; OFF                       ; Untyped                    ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                    ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                    ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                    ;
; BANDWIDTH                     ; 0                         ; Untyped                    ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                    ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                    ;
; DOWN_SPREAD                   ; 0                         ; Untyped                    ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                    ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                    ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                    ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                    ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                    ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                    ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                    ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                    ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                    ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                    ;
; CLK1_MULTIPLY_BY              ; 1                         ; Signed Integer             ;
; CLK0_MULTIPLY_BY              ; 1                         ; Signed Integer             ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                    ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                    ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                    ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                    ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                    ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                    ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                    ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                    ;
; CLK1_DIVIDE_BY                ; 12500                     ; Signed Integer             ;
; CLK0_DIVIDE_BY                ; 5000                      ; Signed Integer             ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                    ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                    ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                    ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                    ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                    ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                    ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                    ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                    ;
; CLK1_DUTY_CYCLE               ; 50                        ; Signed Integer             ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer             ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                    ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                    ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                    ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                    ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                    ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                    ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                    ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                    ;
; DPA_DIVIDER                   ; 0                         ; Untyped                    ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                    ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                    ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                    ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                    ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                    ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                    ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                    ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                    ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                    ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                    ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                    ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                    ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                    ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                    ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                    ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                    ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                    ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                    ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                    ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                    ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                    ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                    ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                    ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                    ;
; VCO_MIN                       ; 0                         ; Untyped                    ;
; VCO_MAX                       ; 0                         ; Untyped                    ;
; VCO_CENTER                    ; 0                         ; Untyped                    ;
; PFD_MIN                       ; 0                         ; Untyped                    ;
; PFD_MAX                       ; 0                         ; Untyped                    ;
; M_INITIAL                     ; 0                         ; Untyped                    ;
; M                             ; 0                         ; Untyped                    ;
; N                             ; 1                         ; Untyped                    ;
; M2                            ; 1                         ; Untyped                    ;
; N2                            ; 1                         ; Untyped                    ;
; SS                            ; 1                         ; Untyped                    ;
; C0_HIGH                       ; 0                         ; Untyped                    ;
; C1_HIGH                       ; 0                         ; Untyped                    ;
; C2_HIGH                       ; 0                         ; Untyped                    ;
; C3_HIGH                       ; 0                         ; Untyped                    ;
; C4_HIGH                       ; 0                         ; Untyped                    ;
; C5_HIGH                       ; 0                         ; Untyped                    ;
; C6_HIGH                       ; 0                         ; Untyped                    ;
; C7_HIGH                       ; 0                         ; Untyped                    ;
; C8_HIGH                       ; 0                         ; Untyped                    ;
; C9_HIGH                       ; 0                         ; Untyped                    ;
; C0_LOW                        ; 0                         ; Untyped                    ;
; C1_LOW                        ; 0                         ; Untyped                    ;
; C2_LOW                        ; 0                         ; Untyped                    ;
; C3_LOW                        ; 0                         ; Untyped                    ;
; C4_LOW                        ; 0                         ; Untyped                    ;
; C5_LOW                        ; 0                         ; Untyped                    ;
; C6_LOW                        ; 0                         ; Untyped                    ;
; C7_LOW                        ; 0                         ; Untyped                    ;
; C8_LOW                        ; 0                         ; Untyped                    ;
; C9_LOW                        ; 0                         ; Untyped                    ;
; C0_INITIAL                    ; 0                         ; Untyped                    ;
; C1_INITIAL                    ; 0                         ; Untyped                    ;
; C2_INITIAL                    ; 0                         ; Untyped                    ;
; C3_INITIAL                    ; 0                         ; Untyped                    ;
; C4_INITIAL                    ; 0                         ; Untyped                    ;
; C5_INITIAL                    ; 0                         ; Untyped                    ;
; C6_INITIAL                    ; 0                         ; Untyped                    ;
; C7_INITIAL                    ; 0                         ; Untyped                    ;
; C8_INITIAL                    ; 0                         ; Untyped                    ;
; C9_INITIAL                    ; 0                         ; Untyped                    ;
; C0_MODE                       ; BYPASS                    ; Untyped                    ;
; C1_MODE                       ; BYPASS                    ; Untyped                    ;
; C2_MODE                       ; BYPASS                    ; Untyped                    ;
; C3_MODE                       ; BYPASS                    ; Untyped                    ;
; C4_MODE                       ; BYPASS                    ; Untyped                    ;
; C5_MODE                       ; BYPASS                    ; Untyped                    ;
; C6_MODE                       ; BYPASS                    ; Untyped                    ;
; C7_MODE                       ; BYPASS                    ; Untyped                    ;
; C8_MODE                       ; BYPASS                    ; Untyped                    ;
; C9_MODE                       ; BYPASS                    ; Untyped                    ;
; C0_PH                         ; 0                         ; Untyped                    ;
; C1_PH                         ; 0                         ; Untyped                    ;
; C2_PH                         ; 0                         ; Untyped                    ;
; C3_PH                         ; 0                         ; Untyped                    ;
; C4_PH                         ; 0                         ; Untyped                    ;
; C5_PH                         ; 0                         ; Untyped                    ;
; C6_PH                         ; 0                         ; Untyped                    ;
; C7_PH                         ; 0                         ; Untyped                    ;
; C8_PH                         ; 0                         ; Untyped                    ;
; C9_PH                         ; 0                         ; Untyped                    ;
; L0_HIGH                       ; 1                         ; Untyped                    ;
; L1_HIGH                       ; 1                         ; Untyped                    ;
; G0_HIGH                       ; 1                         ; Untyped                    ;
; G1_HIGH                       ; 1                         ; Untyped                    ;
; G2_HIGH                       ; 1                         ; Untyped                    ;
; G3_HIGH                       ; 1                         ; Untyped                    ;
; E0_HIGH                       ; 1                         ; Untyped                    ;
; E1_HIGH                       ; 1                         ; Untyped                    ;
; E2_HIGH                       ; 1                         ; Untyped                    ;
; E3_HIGH                       ; 1                         ; Untyped                    ;
; L0_LOW                        ; 1                         ; Untyped                    ;
; L1_LOW                        ; 1                         ; Untyped                    ;
; G0_LOW                        ; 1                         ; Untyped                    ;
; G1_LOW                        ; 1                         ; Untyped                    ;
; G2_LOW                        ; 1                         ; Untyped                    ;
; G3_LOW                        ; 1                         ; Untyped                    ;
; E0_LOW                        ; 1                         ; Untyped                    ;
; E1_LOW                        ; 1                         ; Untyped                    ;
; E2_LOW                        ; 1                         ; Untyped                    ;
; E3_LOW                        ; 1                         ; Untyped                    ;
; L0_INITIAL                    ; 1                         ; Untyped                    ;
; L1_INITIAL                    ; 1                         ; Untyped                    ;
; G0_INITIAL                    ; 1                         ; Untyped                    ;
; G1_INITIAL                    ; 1                         ; Untyped                    ;
; G2_INITIAL                    ; 1                         ; Untyped                    ;
; G3_INITIAL                    ; 1                         ; Untyped                    ;
; E0_INITIAL                    ; 1                         ; Untyped                    ;
; E1_INITIAL                    ; 1                         ; Untyped                    ;
; E2_INITIAL                    ; 1                         ; Untyped                    ;
; E3_INITIAL                    ; 1                         ; Untyped                    ;
; L0_MODE                       ; BYPASS                    ; Untyped                    ;
; L1_MODE                       ; BYPASS                    ; Untyped                    ;
; G0_MODE                       ; BYPASS                    ; Untyped                    ;
; G1_MODE                       ; BYPASS                    ; Untyped                    ;
; G2_MODE                       ; BYPASS                    ; Untyped                    ;
; G3_MODE                       ; BYPASS                    ; Untyped                    ;
; E0_MODE                       ; BYPASS                    ; Untyped                    ;
; E1_MODE                       ; BYPASS                    ; Untyped                    ;
; E2_MODE                       ; BYPASS                    ; Untyped                    ;
; E3_MODE                       ; BYPASS                    ; Untyped                    ;
; L0_PH                         ; 0                         ; Untyped                    ;
; L1_PH                         ; 0                         ; Untyped                    ;
; G0_PH                         ; 0                         ; Untyped                    ;
; G1_PH                         ; 0                         ; Untyped                    ;
; G2_PH                         ; 0                         ; Untyped                    ;
; G3_PH                         ; 0                         ; Untyped                    ;
; E0_PH                         ; 0                         ; Untyped                    ;
; E1_PH                         ; 0                         ; Untyped                    ;
; E2_PH                         ; 0                         ; Untyped                    ;
; E3_PH                         ; 0                         ; Untyped                    ;
; M_PH                          ; 0                         ; Untyped                    ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                    ;
; CLK0_COUNTER                  ; G0                        ; Untyped                    ;
; CLK1_COUNTER                  ; G0                        ; Untyped                    ;
; CLK2_COUNTER                  ; G0                        ; Untyped                    ;
; CLK3_COUNTER                  ; G0                        ; Untyped                    ;
; CLK4_COUNTER                  ; G0                        ; Untyped                    ;
; CLK5_COUNTER                  ; G0                        ; Untyped                    ;
; CLK6_COUNTER                  ; E0                        ; Untyped                    ;
; CLK7_COUNTER                  ; E1                        ; Untyped                    ;
; CLK8_COUNTER                  ; E2                        ; Untyped                    ;
; CLK9_COUNTER                  ; E3                        ; Untyped                    ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                    ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                    ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                    ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                    ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                    ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                    ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                    ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                    ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                    ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                    ;
; M_TIME_DELAY                  ; 0                         ; Untyped                    ;
; N_TIME_DELAY                  ; 0                         ; Untyped                    ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                    ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                    ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                    ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                    ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                    ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                    ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                    ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                    ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                    ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                    ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                    ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                    ;
; VCO_POST_SCALE                ; 0                         ; Untyped                    ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                    ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                    ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                    ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E              ; Untyped                    ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                    ;
; PORT_CLK1                     ; PORT_USED                 ; Untyped                    ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                    ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                    ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                    ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                    ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                    ;
; PORT_ARESET                   ; PORT_USED                 ; Untyped                    ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                    ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                    ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                    ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                    ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                    ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                    ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                    ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                    ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                    ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                    ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                    ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                    ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                    ;
; CBXI_PARAMETER                ; lab3pll_altpll            ; Untyped                    ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                    ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                    ;
; WIDTH_CLOCK                   ; 5                         ; Signed Integer             ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                    ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                    ;
; DEVICE_FAMILY                 ; Cyclone IV E              ; Untyped                    ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                    ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                    ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE             ;
+-------------------------------+---------------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                              ;
+-------------------------------+-------------------------------------------+
; Name                          ; Value                                     ;
+-------------------------------+-------------------------------------------+
; Number of entity instances    ; 1                                         ;
; Entity Instance               ; lab3pll:lab3pll_0|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                    ;
;     -- PLL_TYPE               ; AUTO                                      ;
;     -- PRIMARY_CLOCK          ; INCLK0                                    ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                     ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                         ;
;     -- VCO_MULTIPLY_BY        ; 0                                         ;
;     -- VCO_DIVIDE_BY          ; 0                                         ;
+-------------------------------+-------------------------------------------+


+--------------------------------------------------------+
; Port Connectivity Checks: "bcd_updn:bcd_updn_d2"       ;
+-----------+--------+----------+------------------------+
; Port      ; Type   ; Severity ; Details                ;
+-----------+--------+----------+------------------------+
; carry_out ; Output ; Info     ; Explicitly unconnected ;
+-----------+--------+----------+------------------------+


+--------------------------------------------------+
; Port Connectivity Checks: "bcd_updn:bcd_updn_d0" ;
+----------+-------+----------+--------------------+
; Port     ; Type  ; Severity ; Details            ;
+----------+-------+----------+--------------------+
; carry_in ; Input ; Info     ; Stuck at VCC       ;
+----------+-------+----------+--------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 19                          ;
; cycloneiii_ff         ; 51                          ;
;     CLR               ; 31                          ;
;     CLR SCLR          ; 1                           ;
;     ENA CLR           ; 2                           ;
;     ENA CLR SCLR      ; 8                           ;
;     ENA CLR SLD       ; 9                           ;
; cycloneiii_lcell_comb ; 88                          ;
;     arith             ; 16                          ;
;         2 data inputs ; 10                          ;
;         3 data inputs ; 6                           ;
;     normal            ; 72                          ;
;         0 data inputs ; 2                           ;
;         1 data inputs ; 6                           ;
;         2 data inputs ; 18                          ;
;         3 data inputs ; 17                          ;
;         4 data inputs ; 29                          ;
; cycloneiii_pll        ; 1                           ;
;                       ;                             ;
; Max LUT depth         ; 4.00                        ;
; Average LUT depth     ; 2.25                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition
    Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, the Altera Quartus Prime License Agreement,
    Info: the Altera MegaCore Function License Agreement, or other 
    Info: applicable license agreement, including, without limitation, 
    Info: that your use is for the sole purpose of programming logic 
    Info: devices manufactured by Altera and sold by Altera or its 
    Info: authorized distributors.  Please refer to the applicable 
    Info: agreement for further details.
    Info: Processing started: Fri Apr 29 15:20:23 2016
Info: Command: quartus_map lab3 --source=lab3.sv --source=debouncer.sv --source=quad_decode.sv --source=bcd2_7seg.sv --source=bcd_updn.sv --source=pll/lab3pll.v --family="Cyclone IV E"
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file lab3.sv
    Info (12023): Found entity 1: lab3 File: /home/traylor/fpga/lab3/lab3.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file debouncer.sv
    Info (12023): Found entity 1: debouncer File: /home/traylor/fpga/lab3/debouncer.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file quad_decode.sv
    Info (12023): Found entity 1: quad_decode File: /home/traylor/fpga/lab3/quad_decode.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file bcd2_7seg.sv
    Info (12023): Found entity 1: bcd2_7seg File: /home/traylor/fpga/lab3/bcd2_7seg.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file bcd_updn.sv
    Info (12023): Found entity 1: bcd_updn File: /home/traylor/fpga/lab3/bcd_updn.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file pll/lab3pll.v
    Info (12023): Found entity 1: lab3pll File: /home/traylor/fpga/lab3/pll/lab3pll.v Line: 40
Info (12127): Elaborating entity "lab3" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at lab3.sv(56): object "new_var" assigned a value but never read File: /home/traylor/fpga/lab3/lab3.sv Line: 56
Info (12128): Elaborating entity "debouncer" for hierarchy "debouncer:debounce_enc_a" File: /home/traylor/fpga/lab3/lab3.sv Line: 66
Info (12128): Elaborating entity "quad_decode" for hierarchy "quad_decode:quad_decode_0" File: /home/traylor/fpga/lab3/lab3.sv Line: 80
Info (12128): Elaborating entity "bcd_updn" for hierarchy "bcd_updn:bcd_updn_d0" File: /home/traylor/fpga/lab3/lab3.sv Line: 110
Info (12128): Elaborating entity "bcd2_7seg" for hierarchy "bcd2_7seg:bcd2_7seg_0" File: /home/traylor/fpga/lab3/lab3.sv Line: 133
Warning (10958): SystemVerilog warning at bcd2_7seg.sv(11): unique or priority keyword makes case statement complete File: /home/traylor/fpga/lab3/bcd2_7seg.sv Line: 11
Info (12128): Elaborating entity "lab3pll" for hierarchy "lab3pll:lab3pll_0" File: /home/traylor/fpga/lab3/lab3.sv Line: 175
Info (12128): Elaborating entity "altpll" for hierarchy "lab3pll:lab3pll_0|altpll:altpll_component" File: /home/traylor/fpga/lab3/pll/lab3pll.v Line: 104
Info (12130): Elaborated megafunction instantiation "lab3pll:lab3pll_0|altpll:altpll_component" File: /home/traylor/fpga/lab3/pll/lab3pll.v Line: 104
Info (12133): Instantiated megafunction "lab3pll:lab3pll_0|altpll:altpll_component" with the following parameter: File: /home/traylor/fpga/lab3/pll/lab3pll.v Line: 104
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "5000"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "12500"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=lab3pll"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_USED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/lab3pll_altpll.v
    Info (12023): Found entity 1: lab3pll_altpll File: /home/traylor/fpga/lab3/db/lab3pll_altpll.v Line: 30
Info (12128): Elaborating entity "lab3pll_altpll" for hierarchy "lab3pll:lab3pll_0|altpll:altpll_component|lab3pll_altpll:auto_generated" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "segment_data[0]" is stuck at VCC File: /home/traylor/fpga/lab3/lab3.sv Line: 6
    Warning (13410): Pin "sel2" is stuck at GND File: /home/traylor/fpga/lab3/lab3.sv Line: 9
    Warning (13410): Pin "enable3to8_n" is stuck at GND File: /home/traylor/fpga/lab3/lab3.sv Line: 11
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 118 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 5 input pins
    Info (21059): Implemented 14 output pins
    Info (21061): Implemented 98 logic cells
    Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 1196 megabytes
    Info: Processing ended: Fri Apr 29 15:20:36 2016
    Info: Elapsed time: 00:00:13
    Info: Total CPU time (on all processors): 00:00:21


