EDA Netlist Writer report for lab5 Fri May 6 14:24:23 2016 Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. EDA Netlist Writer Summary 3. Simulation Settings 4. Simulation Generated Files 5. EDA Netlist Writer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ ; EDA Netlist Writer Status ; Successful - Fri May 6 14:24:23 2016 ; ; Revision Name ; lab5 ; ; Top-level Entity Name ; lab5 ; ; Family ; Cyclone IV E ; ; Simulation Files Creation ; Successful ; +---------------------------+---------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------+ ; Simulation Settings ; +---------------------------------------------------------------------------------------------------+---------------------------------+ ; Option ; Setting ; +---------------------------------------------------------------------------------------------------+---------------------------------+ ; Tool Name ; ModelSim-Altera (SystemVerilog) ; ; Generate netlist for functional simulation only ; Off ; ; Time scale ; 1 ps ; ; Truncate long hierarchy paths ; Off ; ; Map illegal HDL characters ; Off ; ; Flatten buses into individual nodes ; Off ; ; Maintain hierarchy ; Off ; ; Bring out device-wide set/reset signals as ports ; Off ; ; Enable glitch filtering ; Off ; ; Do not write top level VHDL entity ; Off ; ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; ; Architecture name in VHDL output netlist ; structure ; ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; ; Generate third-party EDA tool command script for gate-level simulation ; Off ; +---------------------------------------------------------------------------------------------------+---------------------------------+ +---------------------------------------------------------------------------+ ; Simulation Generated Files ; +---------------------------------------------------------------------------+ ; Generated Files ; +---------------------------------------------------------------------------+ ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_6_1200mv_85c_slow.svo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_6_1200mv_0c_slow.svo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_min_1200mv_0c_fast.svo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5.svo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_6_1200mv_85c_v_slow.sdo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_6_1200mv_0c_v_slow.sdo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_min_1200mv_0c_v_fast.sdo ; ; /home/traylor/fpga/lab5/simulation/modelsim/lab5_v.sdo ; +---------------------------------------------------------------------------+ +-----------------------------+ ; EDA Netlist Writer Messages ; +-----------------------------+ Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition Info: Processing started: Fri May 6 14:24:22 2016 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off lab5 -c lab5 Info (204019): Generated file lab5_6_1200mv_85c_slow.svo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5_6_1200mv_0c_slow.svo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5_min_1200mv_0c_fast.svo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5.svo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5_6_1200mv_85c_v_slow.sdo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5_6_1200mv_0c_v_slow.sdo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5_min_1200mv_0c_v_fast.sdo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file lab5_v.sdo in folder "/home/traylor/fpga/lab5/simulation/modelsim/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1260 megabytes Info: Processing ended: Fri May 6 14:24:23 2016 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01