Analysis & Synthesis report for lab5
Fri May  6 14:23:49 2016
Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Registers Packed Into Inferred Megafunctions
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0|altsyncram_ct61:auto_generated
 14. Parameter Settings for User Entity Instance: pll_lab5:pll_lab5_inst|altpll:altpll_component
 15. Parameter Settings for Inferred Entity Instance: sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0
 16. altpll Parameter Settings by Entity Instance
 17. altsyncram Parameter Settings by Entity Instance
 18. Port Connectivity Checks: "pll_lab5:pll_lab5_inst"
 19. Post-Synthesis Netlist Statistics for Top Partition
 20. Elapsed Time Per Partition
 21. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri May  6 14:23:49 2016       ;
; Quartus Prime Version              ; 15.1.1 Build 189 12/02/2015 SJ Lite Edition ;
; Revision Name                      ; lab5                                        ;
; Top-level Entity Name              ; lab5                                        ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 231                                         ;
;     Total combinational functions  ; 221                                         ;
;     Dedicated logic registers      ; 56                                          ;
; Total registers                    ; 56                                          ;
; Total pins                         ; 26                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 16,384                                      ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22F17C6       ;                    ;
; Top-level entity name                                                      ; lab5               ; lab5               ;
; Family name                                                                ; Cyclone IV E       ; Cyclone V          ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                            ;
+----------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path       ; Used in Netlist ; File Type                                             ; File Name with Absolute Path                                                         ; Library ;
+----------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------------------------+---------+
; lab5.sv                                ; yes             ; User SystemVerilog HDL File                           ; /home/traylor/fpga/lab5/lab5.sv                                                      ;         ;
; debouncer.sv                           ; yes             ; User SystemVerilog HDL File                           ; /home/traylor/fpga/lab5/debouncer.sv                                                 ;         ;
; quad_decode.sv                         ; yes             ; User SystemVerilog HDL File                           ; /home/traylor/fpga/lab5/quad_decode.sv                                               ;         ;
; bcd2_7seg.sv                           ; yes             ; User SystemVerilog HDL File                           ; /home/traylor/fpga/lab5/bcd2_7seg.sv                                                 ;         ;
; pll_lab5/pll_lab5.v                    ; yes             ; User Wizard-Generated File                            ; /home/traylor/fpga/lab5/pll_lab5/pll_lab5.v                                          ;         ;
; sine_rom.sv                            ; yes             ; User SystemVerilog HDL File                           ; /home/traylor/fpga/lab5/sine_rom.sv                                                  ;         ;
; cntr_updn_14bit.sv                     ; yes             ; Auto-Found SystemVerilog HDL File                     ; /home/traylor/fpga/lab5/cntr_updn_14bit.sv                                           ;         ;
; bin2bcd.sv                             ; yes             ; Auto-Found SystemVerilog HDL File                     ; /home/traylor/fpga/lab5/bin2bcd.sv                                                   ;         ;
; altpll.tdf                             ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf            ;         ;
; aglobal151.inc                         ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/aglobal151.inc        ;         ;
; stratix_pll.inc                        ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratix_pll.inc       ;         ;
; stratixii_pll.inc                      ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratixii_pll.inc     ;         ;
; cycloneii_pll.inc                      ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/cycloneii_pll.inc     ;         ;
; db/pll_lab5_altpll.v                   ; yes             ; Auto-Generated Megafunction                           ; /home/traylor/fpga/lab5/db/pll_lab5_altpll.v                                         ;         ;
; altsyncram.tdf                         ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altsyncram.tdf        ;         ;
; stratix_ram_block.inc                  ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratix_ram_block.inc ;         ;
; lpm_mux.inc                            ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_mux.inc           ;         ;
; lpm_decode.inc                         ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_decode.inc        ;         ;
; a_rdenreg.inc                          ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/a_rdenreg.inc         ;         ;
; altrom.inc                             ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altrom.inc            ;         ;
; altram.inc                             ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altram.inc            ;         ;
; altdpram.inc                           ; yes             ; Megafunction                                          ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altdpram.inc          ;         ;
; db/altsyncram_ct61.tdf                 ; yes             ; Auto-Generated Megafunction                           ; /home/traylor/fpga/lab5/db/altsyncram_ct61.tdf                                       ;         ;
; db/lab5.rom0_sine_rom_d6b5acbf.hdl.mif ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; /home/traylor/fpga/lab5/db/lab5.rom0_sine_rom_d6b5acbf.hdl.mif                       ;         ;
+----------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Estimated Total logic elements              ; 231           ;
;                                             ;               ;
; Total combinational functions               ; 221           ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 136           ;
;     -- 3 input functions                    ; 37            ;
;     -- <=2 input functions                  ; 48            ;
;                                             ;               ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 172           ;
;     -- arithmetic mode                      ; 49            ;
;                                             ;               ;
; Total registers                             ; 56            ;
;     -- Dedicated logic registers            ; 56            ;
;     -- I/O registers                        ; 0             ;
;                                             ;               ;
; I/O pins                                    ; 26            ;
; Total memory bits                           ; 16384         ;
;                                             ;               ;
; Embedded Multiplier 9-bit elements          ; 0             ;
;                                             ;               ;
; Total PLLs                                  ; 1             ;
;     -- PLLs                                 ; 1             ;
;                                             ;               ;
; Maximum fan-out node                        ; reset_n~input ;
; Maximum fan-out                             ; 57            ;
; Total fan-out                               ; 1075          ;
; Average fan-out                             ; 3.18          ;
+---------------------------------------------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                        ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                 ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------+--------------+
; |lab5                                     ; 221 (56)          ; 56 (30)      ; 16384       ; 0            ; 0       ; 0         ; 26   ; 0            ; |lab5                                                                               ; work         ;
;    |bcd2_7seg:bcd2_7seg_0|                ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|bcd2_7seg:bcd2_7seg_0                                                         ; work         ;
;    |bin2bcd:bin2bcd_0|                    ; 95 (95)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|bin2bcd:bin2bcd_0                                                             ; work         ;
;    |cntr_updn_14bit:cntr_updn_14_bit_0|   ; 57 (57)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|cntr_updn_14bit:cntr_updn_14_bit_0                                            ; work         ;
;    |debouncer:debounce_enc_a|             ; 2 (2)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|debouncer:debounce_enc_a                                                      ; work         ;
;    |debouncer:debounce_enc_b|             ; 2 (2)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|debouncer:debounce_enc_b                                                      ; work         ;
;    |pll_lab5:pll_lab5_inst|               ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|pll_lab5:pll_lab5_inst                                                        ; work         ;
;       |altpll:altpll_component|           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|pll_lab5:pll_lab5_inst|altpll:altpll_component                                ; work         ;
;          |pll_lab5_altpll:auto_generated| ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|pll_lab5:pll_lab5_inst|altpll:altpll_component|pll_lab5_altpll:auto_generated ; work         ;
;    |quad_decode:quad_decode_0|            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|quad_decode:quad_decode_0                                                     ; work         ;
;    |sine_rom:sine_rom_0|                  ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|sine_rom:sine_rom_0                                                           ; work         ;
;       |altsyncram:Ram0_rtl_0|             ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0                                     ; work         ;
;          |altsyncram_ct61:auto_generated| ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab5|sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0|altsyncram_ct61:auto_generated      ; work         ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                               ;
+-------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------------------------------------+
; Name                                                                                ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                                    ;
+-------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------------------------------------+
; sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0|altsyncram_ct61:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 2048         ; 8            ; --           ; --           ; 16384 ; db/lab5.rom0_sine_rom_d6b5acbf.hdl.mif ;
+-------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 56    ;
; Number of registers using Synchronous Clear  ; 1     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 56    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 14    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------+
; Inverted Register Statistics                              ;
+-------------------------------------------------+---------+
; Inverted Register                               ; Fan out ;
+-------------------------------------------------+---------+
; cntr_updn_14bit:cntr_updn_14_bit_0|count_out[9] ; 10      ;
; cntr_updn_14bit:cntr_updn_14_bit_0|count_out[8] ; 10      ;
; cntr_updn_14bit:cntr_updn_14_bit_0|count_out[7] ; 9       ;
; cntr_updn_14bit:cntr_updn_14_bit_0|count_out[6] ; 8       ;
; cntr_updn_14bit:cntr_updn_14_bit_0|count_out[5] ; 8       ;
; cntr_updn_14bit:cntr_updn_14_bit_0|count_out[3] ; 9       ;
; Total number of inverted registers = 6          ;         ;
+-------------------------------------------------+---------+


+----------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                               ;
+------------------------------------+--------------------------------+------+
; Register Name                      ; Megafunction                   ; Type ;
+------------------------------------+--------------------------------+------+
; sine_rom:sine_rom_0|sine_val[0..7] ; sine_rom:sine_rom_0|Ram0_rtl_0 ; RAM  ;
+------------------------------------+--------------------------------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |lab5|cntr_updn_14bit:cntr_updn_14_bit_0|count_out[0] ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |lab5|cntr_updn_14bit:cntr_updn_14_bit_0|count_out[7] ;
; 5:1                ; 3 bits    ; 9 LEs         ; 9 LEs                ; 0 LEs                  ; No         ; |lab5|Selector2                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Source assignments for sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0|altsyncram_ct61:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------+
; Assignment                      ; Value              ; From ; To                                ;
+---------------------------------+--------------------+------+-----------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                 ;
+---------------------------------+--------------------+------+-----------------------------------+


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pll_lab5:pll_lab5_inst|altpll:altpll_component ;
+-------------------------------+----------------------------+--------------------------------+
; Parameter Name                ; Value                      ; Type                           ;
+-------------------------------+----------------------------+--------------------------------+
; OPERATION_MODE                ; NORMAL                     ; Untyped                        ;
; PLL_TYPE                      ; AUTO                       ; Untyped                        ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=pll_lab5 ; Untyped                        ;
; QUALIFY_CONF_DONE             ; OFF                        ; Untyped                        ;
; COMPENSATE_CLOCK              ; CLK0                       ; Untyped                        ;
; SCAN_CHAIN                    ; LONG                       ; Untyped                        ;
; PRIMARY_CLOCK                 ; INCLK0                     ; Untyped                        ;
; INCLK0_INPUT_FREQUENCY        ; 20000                      ; Signed Integer                 ;
; INCLK1_INPUT_FREQUENCY        ; 0                          ; Untyped                        ;
; GATE_LOCK_SIGNAL              ; NO                         ; Untyped                        ;
; GATE_LOCK_COUNTER             ; 0                          ; Untyped                        ;
; LOCK_HIGH                     ; 1                          ; Untyped                        ;
; LOCK_LOW                      ; 1                          ; Untyped                        ;
; VALID_LOCK_MULTIPLIER         ; 1                          ; Untyped                        ;
; INVALID_LOCK_MULTIPLIER       ; 5                          ; Untyped                        ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                        ; Untyped                        ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                        ; Untyped                        ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                        ; Untyped                        ;
; SKIP_VCO                      ; OFF                        ; Untyped                        ;
; SWITCH_OVER_COUNTER           ; 0                          ; Untyped                        ;
; SWITCH_OVER_TYPE              ; AUTO                       ; Untyped                        ;
; FEEDBACK_SOURCE               ; EXTCLK0                    ; Untyped                        ;
; BANDWIDTH                     ; 0                          ; Untyped                        ;
; BANDWIDTH_TYPE                ; AUTO                       ; Untyped                        ;
; SPREAD_FREQUENCY              ; 0                          ; Untyped                        ;
; DOWN_SPREAD                   ; 0                          ; Untyped                        ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                        ; Untyped                        ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                        ; Untyped                        ;
; CLK9_MULTIPLY_BY              ; 0                          ; Untyped                        ;
; CLK8_MULTIPLY_BY              ; 0                          ; Untyped                        ;
; CLK7_MULTIPLY_BY              ; 0                          ; Untyped                        ;
; CLK6_MULTIPLY_BY              ; 0                          ; Untyped                        ;
; CLK5_MULTIPLY_BY              ; 1                          ; Untyped                        ;
; CLK4_MULTIPLY_BY              ; 1                          ; Untyped                        ;
; CLK3_MULTIPLY_BY              ; 1                          ; Untyped                        ;
; CLK2_MULTIPLY_BY              ; 131072                     ; Signed Integer                 ;
; CLK1_MULTIPLY_BY              ; 1                          ; Signed Integer                 ;
; CLK0_MULTIPLY_BY              ; 1                          ; Signed Integer                 ;
; CLK9_DIVIDE_BY                ; 0                          ; Untyped                        ;
; CLK8_DIVIDE_BY                ; 0                          ; Untyped                        ;
; CLK7_DIVIDE_BY                ; 0                          ; Untyped                        ;
; CLK6_DIVIDE_BY                ; 0                          ; Untyped                        ;
; CLK5_DIVIDE_BY                ; 1                          ; Untyped                        ;
; CLK4_DIVIDE_BY                ; 1                          ; Untyped                        ;
; CLK3_DIVIDE_BY                ; 1                          ; Untyped                        ;
; CLK2_DIVIDE_BY                ; 390625                     ; Signed Integer                 ;
; CLK1_DIVIDE_BY                ; 12500                      ; Signed Integer                 ;
; CLK0_DIVIDE_BY                ; 5000                       ; Signed Integer                 ;
; CLK9_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK8_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK7_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK6_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK5_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK4_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK3_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK2_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK1_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK0_PHASE_SHIFT              ; 0                          ; Untyped                        ;
; CLK5_TIME_DELAY               ; 0                          ; Untyped                        ;
; CLK4_TIME_DELAY               ; 0                          ; Untyped                        ;
; CLK3_TIME_DELAY               ; 0                          ; Untyped                        ;
; CLK2_TIME_DELAY               ; 0                          ; Untyped                        ;
; CLK1_TIME_DELAY               ; 0                          ; Untyped                        ;
; CLK0_TIME_DELAY               ; 0                          ; Untyped                        ;
; CLK9_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK8_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK7_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK6_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK5_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK4_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK3_DUTY_CYCLE               ; 50                         ; Untyped                        ;
; CLK2_DUTY_CYCLE               ; 50                         ; Signed Integer                 ;
; CLK1_DUTY_CYCLE               ; 50                         ; Signed Integer                 ;
; CLK0_DUTY_CYCLE               ; 50                         ; Signed Integer                 ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                        ; Untyped                        ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                        ; Untyped                        ;
; LOCK_WINDOW_UI                ;  0.05                      ; Untyped                        ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                     ; Untyped                        ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                     ; Untyped                        ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                     ; Untyped                        ;
; DPA_MULTIPLY_BY               ; 0                          ; Untyped                        ;
; DPA_DIVIDE_BY                 ; 1                          ; Untyped                        ;
; DPA_DIVIDER                   ; 0                          ; Untyped                        ;
; EXTCLK3_MULTIPLY_BY           ; 1                          ; Untyped                        ;
; EXTCLK2_MULTIPLY_BY           ; 1                          ; Untyped                        ;
; EXTCLK1_MULTIPLY_BY           ; 1                          ; Untyped                        ;
; EXTCLK0_MULTIPLY_BY           ; 1                          ; Untyped                        ;
; EXTCLK3_DIVIDE_BY             ; 1                          ; Untyped                        ;
; EXTCLK2_DIVIDE_BY             ; 1                          ; Untyped                        ;
; EXTCLK1_DIVIDE_BY             ; 1                          ; Untyped                        ;
; EXTCLK0_DIVIDE_BY             ; 1                          ; Untyped                        ;
; EXTCLK3_PHASE_SHIFT           ; 0                          ; Untyped                        ;
; EXTCLK2_PHASE_SHIFT           ; 0                          ; Untyped                        ;
; EXTCLK1_PHASE_SHIFT           ; 0                          ; Untyped                        ;
; EXTCLK0_PHASE_SHIFT           ; 0                          ; Untyped                        ;
; EXTCLK3_TIME_DELAY            ; 0                          ; Untyped                        ;
; EXTCLK2_TIME_DELAY            ; 0                          ; Untyped                        ;
; EXTCLK1_TIME_DELAY            ; 0                          ; Untyped                        ;
; EXTCLK0_TIME_DELAY            ; 0                          ; Untyped                        ;
; EXTCLK3_DUTY_CYCLE            ; 50                         ; Untyped                        ;
; EXTCLK2_DUTY_CYCLE            ; 50                         ; Untyped                        ;
; EXTCLK1_DUTY_CYCLE            ; 50                         ; Untyped                        ;
; EXTCLK0_DUTY_CYCLE            ; 50                         ; Untyped                        ;
; VCO_MULTIPLY_BY               ; 0                          ; Untyped                        ;
; VCO_DIVIDE_BY                 ; 0                          ; Untyped                        ;
; SCLKOUT0_PHASE_SHIFT          ; 0                          ; Untyped                        ;
; SCLKOUT1_PHASE_SHIFT          ; 0                          ; Untyped                        ;
; VCO_MIN                       ; 0                          ; Untyped                        ;
; VCO_MAX                       ; 0                          ; Untyped                        ;
; VCO_CENTER                    ; 0                          ; Untyped                        ;
; PFD_MIN                       ; 0                          ; Untyped                        ;
; PFD_MAX                       ; 0                          ; Untyped                        ;
; M_INITIAL                     ; 0                          ; Untyped                        ;
; M                             ; 0                          ; Untyped                        ;
; N                             ; 1                          ; Untyped                        ;
; M2                            ; 1                          ; Untyped                        ;
; N2                            ; 1                          ; Untyped                        ;
; SS                            ; 1                          ; Untyped                        ;
; C0_HIGH                       ; 0                          ; Untyped                        ;
; C1_HIGH                       ; 0                          ; Untyped                        ;
; C2_HIGH                       ; 0                          ; Untyped                        ;
; C3_HIGH                       ; 0                          ; Untyped                        ;
; C4_HIGH                       ; 0                          ; Untyped                        ;
; C5_HIGH                       ; 0                          ; Untyped                        ;
; C6_HIGH                       ; 0                          ; Untyped                        ;
; C7_HIGH                       ; 0                          ; Untyped                        ;
; C8_HIGH                       ; 0                          ; Untyped                        ;
; C9_HIGH                       ; 0                          ; Untyped                        ;
; C0_LOW                        ; 0                          ; Untyped                        ;
; C1_LOW                        ; 0                          ; Untyped                        ;
; C2_LOW                        ; 0                          ; Untyped                        ;
; C3_LOW                        ; 0                          ; Untyped                        ;
; C4_LOW                        ; 0                          ; Untyped                        ;
; C5_LOW                        ; 0                          ; Untyped                        ;
; C6_LOW                        ; 0                          ; Untyped                        ;
; C7_LOW                        ; 0                          ; Untyped                        ;
; C8_LOW                        ; 0                          ; Untyped                        ;
; C9_LOW                        ; 0                          ; Untyped                        ;
; C0_INITIAL                    ; 0                          ; Untyped                        ;
; C1_INITIAL                    ; 0                          ; Untyped                        ;
; C2_INITIAL                    ; 0                          ; Untyped                        ;
; C3_INITIAL                    ; 0                          ; Untyped                        ;
; C4_INITIAL                    ; 0                          ; Untyped                        ;
; C5_INITIAL                    ; 0                          ; Untyped                        ;
; C6_INITIAL                    ; 0                          ; Untyped                        ;
; C7_INITIAL                    ; 0                          ; Untyped                        ;
; C8_INITIAL                    ; 0                          ; Untyped                        ;
; C9_INITIAL                    ; 0                          ; Untyped                        ;
; C0_MODE                       ; BYPASS                     ; Untyped                        ;
; C1_MODE                       ; BYPASS                     ; Untyped                        ;
; C2_MODE                       ; BYPASS                     ; Untyped                        ;
; C3_MODE                       ; BYPASS                     ; Untyped                        ;
; C4_MODE                       ; BYPASS                     ; Untyped                        ;
; C5_MODE                       ; BYPASS                     ; Untyped                        ;
; C6_MODE                       ; BYPASS                     ; Untyped                        ;
; C7_MODE                       ; BYPASS                     ; Untyped                        ;
; C8_MODE                       ; BYPASS                     ; Untyped                        ;
; C9_MODE                       ; BYPASS                     ; Untyped                        ;
; C0_PH                         ; 0                          ; Untyped                        ;
; C1_PH                         ; 0                          ; Untyped                        ;
; C2_PH                         ; 0                          ; Untyped                        ;
; C3_PH                         ; 0                          ; Untyped                        ;
; C4_PH                         ; 0                          ; Untyped                        ;
; C5_PH                         ; 0                          ; Untyped                        ;
; C6_PH                         ; 0                          ; Untyped                        ;
; C7_PH                         ; 0                          ; Untyped                        ;
; C8_PH                         ; 0                          ; Untyped                        ;
; C9_PH                         ; 0                          ; Untyped                        ;
; L0_HIGH                       ; 1                          ; Untyped                        ;
; L1_HIGH                       ; 1                          ; Untyped                        ;
; G0_HIGH                       ; 1                          ; Untyped                        ;
; G1_HIGH                       ; 1                          ; Untyped                        ;
; G2_HIGH                       ; 1                          ; Untyped                        ;
; G3_HIGH                       ; 1                          ; Untyped                        ;
; E0_HIGH                       ; 1                          ; Untyped                        ;
; E1_HIGH                       ; 1                          ; Untyped                        ;
; E2_HIGH                       ; 1                          ; Untyped                        ;
; E3_HIGH                       ; 1                          ; Untyped                        ;
; L0_LOW                        ; 1                          ; Untyped                        ;
; L1_LOW                        ; 1                          ; Untyped                        ;
; G0_LOW                        ; 1                          ; Untyped                        ;
; G1_LOW                        ; 1                          ; Untyped                        ;
; G2_LOW                        ; 1                          ; Untyped                        ;
; G3_LOW                        ; 1                          ; Untyped                        ;
; E0_LOW                        ; 1                          ; Untyped                        ;
; E1_LOW                        ; 1                          ; Untyped                        ;
; E2_LOW                        ; 1                          ; Untyped                        ;
; E3_LOW                        ; 1                          ; Untyped                        ;
; L0_INITIAL                    ; 1                          ; Untyped                        ;
; L1_INITIAL                    ; 1                          ; Untyped                        ;
; G0_INITIAL                    ; 1                          ; Untyped                        ;
; G1_INITIAL                    ; 1                          ; Untyped                        ;
; G2_INITIAL                    ; 1                          ; Untyped                        ;
; G3_INITIAL                    ; 1                          ; Untyped                        ;
; E0_INITIAL                    ; 1                          ; Untyped                        ;
; E1_INITIAL                    ; 1                          ; Untyped                        ;
; E2_INITIAL                    ; 1                          ; Untyped                        ;
; E3_INITIAL                    ; 1                          ; Untyped                        ;
; L0_MODE                       ; BYPASS                     ; Untyped                        ;
; L1_MODE                       ; BYPASS                     ; Untyped                        ;
; G0_MODE                       ; BYPASS                     ; Untyped                        ;
; G1_MODE                       ; BYPASS                     ; Untyped                        ;
; G2_MODE                       ; BYPASS                     ; Untyped                        ;
; G3_MODE                       ; BYPASS                     ; Untyped                        ;
; E0_MODE                       ; BYPASS                     ; Untyped                        ;
; E1_MODE                       ; BYPASS                     ; Untyped                        ;
; E2_MODE                       ; BYPASS                     ; Untyped                        ;
; E3_MODE                       ; BYPASS                     ; Untyped                        ;
; L0_PH                         ; 0                          ; Untyped                        ;
; L1_PH                         ; 0                          ; Untyped                        ;
; G0_PH                         ; 0                          ; Untyped                        ;
; G1_PH                         ; 0                          ; Untyped                        ;
; G2_PH                         ; 0                          ; Untyped                        ;
; G3_PH                         ; 0                          ; Untyped                        ;
; E0_PH                         ; 0                          ; Untyped                        ;
; E1_PH                         ; 0                          ; Untyped                        ;
; E2_PH                         ; 0                          ; Untyped                        ;
; E3_PH                         ; 0                          ; Untyped                        ;
; M_PH                          ; 0                          ; Untyped                        ;
; C1_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C2_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C3_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C4_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C5_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C6_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C7_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C8_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; C9_USE_CASC_IN                ; OFF                        ; Untyped                        ;
; CLK0_COUNTER                  ; G0                         ; Untyped                        ;
; CLK1_COUNTER                  ; G0                         ; Untyped                        ;
; CLK2_COUNTER                  ; G0                         ; Untyped                        ;
; CLK3_COUNTER                  ; G0                         ; Untyped                        ;
; CLK4_COUNTER                  ; G0                         ; Untyped                        ;
; CLK5_COUNTER                  ; G0                         ; Untyped                        ;
; CLK6_COUNTER                  ; E0                         ; Untyped                        ;
; CLK7_COUNTER                  ; E1                         ; Untyped                        ;
; CLK8_COUNTER                  ; E2                         ; Untyped                        ;
; CLK9_COUNTER                  ; E3                         ; Untyped                        ;
; L0_TIME_DELAY                 ; 0                          ; Untyped                        ;
; L1_TIME_DELAY                 ; 0                          ; Untyped                        ;
; G0_TIME_DELAY                 ; 0                          ; Untyped                        ;
; G1_TIME_DELAY                 ; 0                          ; Untyped                        ;
; G2_TIME_DELAY                 ; 0                          ; Untyped                        ;
; G3_TIME_DELAY                 ; 0                          ; Untyped                        ;
; E0_TIME_DELAY                 ; 0                          ; Untyped                        ;
; E1_TIME_DELAY                 ; 0                          ; Untyped                        ;
; E2_TIME_DELAY                 ; 0                          ; Untyped                        ;
; E3_TIME_DELAY                 ; 0                          ; Untyped                        ;
; M_TIME_DELAY                  ; 0                          ; Untyped                        ;
; N_TIME_DELAY                  ; 0                          ; Untyped                        ;
; EXTCLK3_COUNTER               ; E3                         ; Untyped                        ;
; EXTCLK2_COUNTER               ; E2                         ; Untyped                        ;
; EXTCLK1_COUNTER               ; E1                         ; Untyped                        ;
; EXTCLK0_COUNTER               ; E0                         ; Untyped                        ;
; ENABLE0_COUNTER               ; L0                         ; Untyped                        ;
; ENABLE1_COUNTER               ; L0                         ; Untyped                        ;
; CHARGE_PUMP_CURRENT           ; 2                          ; Untyped                        ;
; LOOP_FILTER_R                 ;  1.000000                  ; Untyped                        ;
; LOOP_FILTER_C                 ; 5                          ; Untyped                        ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                       ; Untyped                        ;
; LOOP_FILTER_R_BITS            ; 9999                       ; Untyped                        ;
; LOOP_FILTER_C_BITS            ; 9999                       ; Untyped                        ;
; VCO_POST_SCALE                ; 0                          ; Untyped                        ;
; CLK2_OUTPUT_FREQUENCY         ; 0                          ; Untyped                        ;
; CLK1_OUTPUT_FREQUENCY         ; 0                          ; Untyped                        ;
; CLK0_OUTPUT_FREQUENCY         ; 0                          ; Untyped                        ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E               ; Untyped                        ;
; PORT_CLKENA0                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKENA1                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKENA2                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKENA3                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKENA4                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKENA5                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_EXTCLK0                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_EXTCLK1                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_EXTCLK2                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_EXTCLK3                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKBAD0                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKBAD1                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK0                     ; PORT_USED                  ; Untyped                        ;
; PORT_CLK1                     ; PORT_USED                  ; Untyped                        ;
; PORT_CLK2                     ; PORT_USED                  ; Untyped                        ;
; PORT_CLK3                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK4                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK5                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK6                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK7                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK8                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLK9                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANDATA                 ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANDATAOUT              ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANDONE                 ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKLOSS                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_INCLK1                   ; PORT_UNUSED                ; Untyped                        ;
; PORT_INCLK0                   ; PORT_USED                  ; Untyped                        ;
; PORT_FBIN                     ; PORT_UNUSED                ; Untyped                        ;
; PORT_PLLENA                   ; PORT_UNUSED                ; Untyped                        ;
; PORT_CLKSWITCH                ; PORT_UNUSED                ; Untyped                        ;
; PORT_ARESET                   ; PORT_USED                  ; Untyped                        ;
; PORT_PFDENA                   ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANCLK                  ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANACLR                 ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANREAD                 ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANWRITE                ; PORT_UNUSED                ; Untyped                        ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_LOCKED                   ; PORT_UNUSED                ; Untyped                        ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED                ; Untyped                        ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_PHASEDONE                ; PORT_UNUSED                ; Untyped                        ;
; PORT_PHASESTEP                ; PORT_UNUSED                ; Untyped                        ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED                ; Untyped                        ;
; PORT_SCANCLKENA               ; PORT_UNUSED                ; Untyped                        ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED                ; Untyped                        ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY          ; Untyped                        ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY          ; Untyped                        ;
; M_TEST_SOURCE                 ; 5                          ; Untyped                        ;
; C0_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C1_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C2_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C3_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C4_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C5_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C6_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C7_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C8_TEST_SOURCE                ; 5                          ; Untyped                        ;
; C9_TEST_SOURCE                ; 5                          ; Untyped                        ;
; CBXI_PARAMETER                ; pll_lab5_altpll            ; Untyped                        ;
; VCO_FREQUENCY_CONTROL         ; AUTO                       ; Untyped                        ;
; VCO_PHASE_SHIFT_STEP          ; 0                          ; Untyped                        ;
; WIDTH_CLOCK                   ; 5                          ; Signed Integer                 ;
; WIDTH_PHASECOUNTERSELECT      ; 4                          ; Untyped                        ;
; USING_FBMIMICBIDIR_PORT       ; OFF                        ; Untyped                        ;
; DEVICE_FAMILY                 ; Cyclone IV E               ; Untyped                        ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                     ; Untyped                        ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                        ; Untyped                        ;
; AUTO_CARRY_CHAINS             ; ON                         ; AUTO_CARRY                     ;
; IGNORE_CARRY_BUFFERS          ; OFF                        ; IGNORE_CARRY                   ;
; AUTO_CASCADE_CHAINS           ; ON                         ; AUTO_CASCADE                   ;
; IGNORE_CASCADE_BUFFERS        ; OFF                        ; IGNORE_CASCADE                 ;
+-------------------------------+----------------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0   ;
+------------------------------------+----------------------------------------+----------------+
; Parameter Name                     ; Value                                  ; Type           ;
+------------------------------------+----------------------------------------+----------------+
; BYTE_SIZE_BLOCK                    ; 8                                      ; Untyped        ;
; AUTO_CARRY_CHAINS                  ; ON                                     ; AUTO_CARRY     ;
; IGNORE_CARRY_BUFFERS               ; OFF                                    ; IGNORE_CARRY   ;
; AUTO_CASCADE_CHAINS                ; ON                                     ; AUTO_CASCADE   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                    ; IGNORE_CASCADE ;
; WIDTH_BYTEENA                      ; 1                                      ; Untyped        ;
; OPERATION_MODE                     ; ROM                                    ; Untyped        ;
; WIDTH_A                            ; 8                                      ; Untyped        ;
; WIDTHAD_A                          ; 11                                     ; Untyped        ;
; NUMWORDS_A                         ; 2048                                   ; Untyped        ;
; OUTDATA_REG_A                      ; UNREGISTERED                           ; Untyped        ;
; ADDRESS_ACLR_A                     ; NONE                                   ; Untyped        ;
; OUTDATA_ACLR_A                     ; NONE                                   ; Untyped        ;
; WRCONTROL_ACLR_A                   ; NONE                                   ; Untyped        ;
; INDATA_ACLR_A                      ; NONE                                   ; Untyped        ;
; BYTEENA_ACLR_A                     ; NONE                                   ; Untyped        ;
; WIDTH_B                            ; 1                                      ; Untyped        ;
; WIDTHAD_B                          ; 1                                      ; Untyped        ;
; NUMWORDS_B                         ; 1                                      ; Untyped        ;
; INDATA_REG_B                       ; CLOCK1                                 ; Untyped        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                 ; Untyped        ;
; RDCONTROL_REG_B                    ; CLOCK1                                 ; Untyped        ;
; ADDRESS_REG_B                      ; CLOCK1                                 ; Untyped        ;
; OUTDATA_REG_B                      ; UNREGISTERED                           ; Untyped        ;
; BYTEENA_REG_B                      ; CLOCK1                                 ; Untyped        ;
; INDATA_ACLR_B                      ; NONE                                   ; Untyped        ;
; WRCONTROL_ACLR_B                   ; NONE                                   ; Untyped        ;
; ADDRESS_ACLR_B                     ; NONE                                   ; Untyped        ;
; OUTDATA_ACLR_B                     ; NONE                                   ; Untyped        ;
; RDCONTROL_ACLR_B                   ; NONE                                   ; Untyped        ;
; BYTEENA_ACLR_B                     ; NONE                                   ; Untyped        ;
; WIDTH_BYTEENA_A                    ; 1                                      ; Untyped        ;
; WIDTH_BYTEENA_B                    ; 1                                      ; Untyped        ;
; RAM_BLOCK_TYPE                     ; AUTO                                   ; Untyped        ;
; BYTE_SIZE                          ; 8                                      ; Untyped        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                              ; Untyped        ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                   ; Untyped        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                   ; Untyped        ;
; INIT_FILE                          ; db/lab5.rom0_sine_rom_d6b5acbf.hdl.mif ; Untyped        ;
; INIT_FILE_LAYOUT                   ; PORT_A                                 ; Untyped        ;
; MAXIMUM_DEPTH                      ; 0                                      ; Untyped        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                                 ; Untyped        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                 ; Untyped        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                                 ; Untyped        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                 ; Untyped        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                        ; Untyped        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                        ; Untyped        ;
; ENABLE_ECC                         ; FALSE                                  ; Untyped        ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                  ; Untyped        ;
; WIDTH_ECCSTATUS                    ; 3                                      ; Untyped        ;
; DEVICE_FAMILY                      ; Cyclone IV E                           ; Untyped        ;
; CBXI_PARAMETER                     ; altsyncram_ct61                        ; Untyped        ;
+------------------------------------+----------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                   ;
+-------------------------------+------------------------------------------------+
; Name                          ; Value                                          ;
+-------------------------------+------------------------------------------------+
; Number of entity instances    ; 1                                              ;
; Entity Instance               ; pll_lab5:pll_lab5_inst|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                         ;
;     -- PLL_TYPE               ; AUTO                                           ;
;     -- PRIMARY_CLOCK          ; INCLK0                                         ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                          ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                              ;
;     -- VCO_MULTIPLY_BY        ; 0                                              ;
;     -- VCO_DIVIDE_BY          ; 0                                              ;
+-------------------------------+------------------------------------------------+


+---------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                      ;
+-------------------------------------------+-------------------------------------------+
; Name                                      ; Value                                     ;
+-------------------------------------------+-------------------------------------------+
; Number of entity instances                ; 1                                         ;
; Entity Instance                           ; sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                       ;
;     -- WIDTH_A                            ; 8                                         ;
;     -- NUMWORDS_A                         ; 2048                                      ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                              ;
;     -- WIDTH_B                            ; 1                                         ;
;     -- NUMWORDS_B                         ; 1                                         ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                    ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                              ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                      ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                 ;
+-------------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "pll_lab5:pll_lab5_inst"                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; c0   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 26                          ;
; cycloneiii_ff         ; 56                          ;
;     CLR               ; 41                          ;
;     CLR SCLR          ; 1                           ;
;     ENA CLR           ; 14                          ;
; cycloneiii_lcell_comb ; 225                         ;
;     arith             ; 49                          ;
;         2 data inputs ; 35                          ;
;         3 data inputs ; 14                          ;
;     normal            ; 176                         ;
;         0 data inputs ; 2                           ;
;         1 data inputs ; 5                           ;
;         2 data inputs ; 10                          ;
;         3 data inputs ; 23                          ;
;         4 data inputs ; 136                         ;
; cycloneiii_pll        ; 1                           ;
; cycloneiii_ram_block  ; 8                           ;
;                       ;                             ;
; Max LUT depth         ; 16.00                       ;
; Average LUT depth     ; 7.75                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:03     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition
    Info: Processing started: Fri May  6 14:23:34 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file lab5.sv
    Info (12023): Found entity 1: lab5 File: /home/traylor/fpga/lab5/lab5.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file debouncer.sv
    Info (12023): Found entity 1: debouncer File: /home/traylor/fpga/lab5/debouncer.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file quad_decode.sv
    Info (12023): Found entity 1: quad_decode File: /home/traylor/fpga/lab5/quad_decode.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file bcd2_7seg.sv
    Info (12023): Found entity 1: bcd2_7seg File: /home/traylor/fpga/lab5/bcd2_7seg.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file bcd_updn.sv
    Info (12023): Found entity 1: bcd_updn File: /home/traylor/fpga/lab5/bcd_updn.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file pll_lab5/pll_lab5.v
    Info (12023): Found entity 1: pll_lab5 File: /home/traylor/fpga/lab5/pll_lab5/pll_lab5.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file sine_rom.sv
    Info (12023): Found entity 1: sine_rom File: /home/traylor/fpga/lab5/sine_rom.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file rom/lab5_rom.v
    Info (12023): Found entity 1: lab5_rom File: /home/traylor/fpga/lab5/rom/lab5_rom.v Line: 40
Info (12127): Elaborating entity "lab5" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at lab5.sv(18): object "logic_one" assigned a value but never read File: /home/traylor/fpga/lab5/lab5.sv Line: 18
Info (12128): Elaborating entity "debouncer" for hierarchy "debouncer:debounce_enc_a" File: /home/traylor/fpga/lab5/lab5.sv Line: 70
Info (12128): Elaborating entity "quad_decode" for hierarchy "quad_decode:quad_decode_0" File: /home/traylor/fpga/lab5/lab5.sv Line: 84
Info (12128): Elaborating entity "sine_rom" for hierarchy "sine_rom:sine_rom_0" File: /home/traylor/fpga/lab5/lab5.sv Line: 90
Warning (12125): Using design file cntr_updn_14bit.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info (12023): Found entity 1: cntr_updn_14bit File: /home/traylor/fpga/lab5/cntr_updn_14bit.sv Line: 1
Info (12128): Elaborating entity "cntr_updn_14bit" for hierarchy "cntr_updn_14bit:cntr_updn_14_bit_0" File: /home/traylor/fpga/lab5/lab5.sv Line: 113
Warning (12125): Using design file bin2bcd.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info (12023): Found entity 1: bin2bcd File: /home/traylor/fpga/lab5/bin2bcd.sv Line: 1
Info (12128): Elaborating entity "bin2bcd" for hierarchy "bin2bcd:bin2bcd_0" File: /home/traylor/fpga/lab5/lab5.sv Line: 120
Warning (10230): Verilog HDL assignment warning at bin2bcd.sv(21): truncated value with size 32 to match size of target (4) File: /home/traylor/fpga/lab5/bin2bcd.sv Line: 21
Warning (10230): Verilog HDL assignment warning at bin2bcd.sv(24): truncated value with size 32 to match size of target (4) File: /home/traylor/fpga/lab5/bin2bcd.sv Line: 24
Warning (10230): Verilog HDL assignment warning at bin2bcd.sv(27): truncated value with size 32 to match size of target (4) File: /home/traylor/fpga/lab5/bin2bcd.sv Line: 27
Warning (10230): Verilog HDL assignment warning at bin2bcd.sv(30): truncated value with size 32 to match size of target (4) File: /home/traylor/fpga/lab5/bin2bcd.sv Line: 30
Info (12128): Elaborating entity "bcd2_7seg" for hierarchy "bcd2_7seg:bcd2_7seg_0" File: /home/traylor/fpga/lab5/lab5.sv Line: 125
Warning (10958): SystemVerilog warning at bcd2_7seg.sv(11): unique or priority keyword makes case statement complete File: /home/traylor/fpga/lab5/bcd2_7seg.sv Line: 11
Info (12128): Elaborating entity "pll_lab5" for hierarchy "pll_lab5:pll_lab5_inst" File: /home/traylor/fpga/lab5/lab5.sv Line: 173
Info (12128): Elaborating entity "altpll" for hierarchy "pll_lab5:pll_lab5_inst|altpll:altpll_component" File: /home/traylor/fpga/lab5/pll_lab5/pll_lab5.v Line: 108
Info (12130): Elaborated megafunction instantiation "pll_lab5:pll_lab5_inst|altpll:altpll_component" File: /home/traylor/fpga/lab5/pll_lab5/pll_lab5.v Line: 108
Info (12133): Instantiated megafunction "pll_lab5:pll_lab5_inst|altpll:altpll_component" with the following parameter: File: /home/traylor/fpga/lab5/pll_lab5/pll_lab5.v Line: 108
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "5000"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "12500"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "clk2_divide_by" = "390625"
    Info (12134): Parameter "clk2_duty_cycle" = "50"
    Info (12134): Parameter "clk2_multiply_by" = "131072"
    Info (12134): Parameter "clk2_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll_lab5"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_USED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_USED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll_lab5_altpll.v
    Info (12023): Found entity 1: pll_lab5_altpll File: /home/traylor/fpga/lab5/db/pll_lab5_altpll.v Line: 30
Info (12128): Elaborating entity "pll_lab5_altpll" for hierarchy "pll_lab5:pll_lab5_inst|altpll:altpll_component|pll_lab5_altpll:auto_generated" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (13014): Ignored 1 buffer(s)
    Info (13019): Ignored 1 SOFT buffer(s)
Info (19000): Inferred 1 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "sine_rom:sine_rom_0|Ram0_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 8
        Info (286033): Parameter WIDTHAD_A set to 11
        Info (286033): Parameter NUMWORDS_A set to 2048
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter INIT_FILE set to db/lab5.rom0_sine_rom_d6b5acbf.hdl.mif
Info (12130): Elaborated megafunction instantiation "sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0"
Info (12133): Instantiated megafunction "sine_rom:sine_rom_0|altsyncram:Ram0_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "8"
    Info (12134): Parameter "WIDTHAD_A" = "11"
    Info (12134): Parameter "NUMWORDS_A" = "2048"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "INIT_FILE" = "db/lab5.rom0_sine_rom_d6b5acbf.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ct61.tdf
    Info (12023): Found entity 1: altsyncram_ct61 File: /home/traylor/fpga/lab5/db/altsyncram_ct61.tdf Line: 28
Info (13000): Registers with preset signals will power-up high File: /home/traylor/fpga/lab5/cntr_updn_14bit.sv Line: 16
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "segment_data[0]" is stuck at VCC File: /home/traylor/fpga/lab5/lab5.sv Line: 5
    Warning (13410): Pin "enable3to8_n" is stuck at GND File: /home/traylor/fpga/lab5/lab5.sv Line: 10
    Warning (13410): Pin "pwm_output" is stuck at GND File: /home/traylor/fpga/lab5/lab5.sv Line: 11
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (15897): PLL "pll_lab5:pll_lab5_inst|altpll:altpll_component|pll_lab5_altpll:auto_generated|pll1" has parameter compensate_clock set to clock0 but port CLK[0] is not connected File: /home/traylor/fpga/lab5/db/pll_lab5_altpll.v Line: 47
Warning (15899): PLL "pll_lab5:pll_lab5_inst|altpll:altpll_component|pll_lab5_altpll:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected File: /home/traylor/fpga/lab5/db/pll_lab5_altpll.v Line: 47
Info (21057): Implemented 268 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 4 input pins
    Info (21059): Implemented 22 output pins
    Info (21061): Implemented 233 logic cells
    Info (21064): Implemented 8 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Peak virtual memory: 1208 megabytes
    Info: Processing ended: Fri May  6 14:23:49 2016
    Info: Elapsed time: 00:00:15
    Info: Total CPU time (on all processors): 00:00:22


