# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition
# Date created = 20:40:30  May 03, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		lab5_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY lab5
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:40:30  MAY 03, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 15.1.1
set_global_assignment -name SOURCE_FILE lab5.sv
set_global_assignment -name SOURCE_FILE debouncer.sv
set_global_assignment -name SOURCE_FILE quad_decode.sv
set_global_assignment -name SOURCE_FILE bcd2_7seg.sv
set_global_assignment -name SOURCE_FILE bcd_updn.sv
set_global_assignment -name SOURCE_FILE pll_lab5/pll_lab5.v
set_global_assignment -name SOURCE_FILE sine_rom.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name QIP_FILE rom/lab5_rom.qip




set_location_assignment PIN_B5 -to enable3to8
set_location_assignment PIN_B4 -to enable3to8_n
set_location_assignment PIN_T15 -to encoder_a
set_location_assignment PIN_T13 -to encoder_b
set_location_assignment PIN_R8 -to inclk0_sig
set_location_assignment PIN_D5 -to pwm_output
set_location_assignment PIN_E1 -to reset_n
set_location_assignment PIN_B12 -to segment_data[7]
set_location_assignment PIN_D11 -to segment_data[6]
set_location_assignment PIN_B11 -to segment_data[5]
set_location_assignment PIN_E10 -to segment_data[4]
set_location_assignment PIN_D9 -to segment_data[3]
set_location_assignment PIN_E9 -to segment_data[2]
set_location_assignment PIN_F8 -to segment_data[1]
set_location_assignment PIN_D8 -to segment_data[0]
set_location_assignment PIN_D3 -to sel0
set_location_assignment PIN_C3 -to sel1
set_location_assignment PIN_A3 -to sel2

set_location_assignment PIN_A5 -to rom_data[0]
set_location_assignment PIN_B6 -to rom_data[1]
set_location_assignment PIN_B7 -to rom_data[2]
set_location_assignment PIN_A7 -to rom_data[3]
set_location_assignment PIN_C8 -to rom_data[4]
set_location_assignment PIN_E7 -to rom_data[5]
set_location_assignment PIN_E8 -to rom_data[6]
set_location_assignment PIN_F9 -to rom_data[7]


set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to encoder_a
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to encoder_b





set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top