# vsim lab5 
# Start time: 14:23:59 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
do do.do
# ** Warning: (vsim-8315) lab5.sv(147): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 1  Instance: /lab5
vlog *.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 14:29:52 on May 05,2016
# vlog -reportprogress 300 bcd2_7seg.sv bcd_updn.sv bin2bcd.sv cntr_updn_14bit.sv debouncer.sv lab5.sv quad_decode.sv sine_rom.sv 
# -- Compiling module bcd2_7seg
# -- Compiling module bcd_updn
# -- Compiling module bin2bcd
# -- Compiling module cntr_updn_14bit
# -- Compiling module debouncer
# -- Compiling module lab5
# -- Compiling module quad_decode
# -- Compiling module sine_rom
# 
# Top level modules:
# 	bcd_updn
# 	lab5
# End time: 14:29:52 on May 05,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim -t ns lab5
# End time: 14:30:02 on May 05,2016, Elapsed time: 0:06:03
# Errors: 0, Warnings: 4
# vsim -t ns lab5 
# Start time: 14:30:02 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
add wave -position insertpoint  \
sim:/lab5/PWM_CYCLE \
sim:/lab5/FOUR_KHZ_CYCLE \
sim:/lab5/CLK16MHZCYCLE \
sim:/lab5/inclk0_sig \
sim:/lab5/encoder_a \
sim:/lab5/encoder_b \
sim:/lab5/segment_data \
sim:/lab5/sel0 \
sim:/lab5/sel1 \
sim:/lab5/sel2 \
sim:/lab5/enable3to8 \
sim:/lab5/enable3to8_n \
sim:/lab5/pwm_output \
sim:/lab5/rom_data \
sim:/lab5/reset_n \
sim:/lab5/logic_one \
sim:/lab5/bcd_cnt_enable \
sim:/lab5/up_d_n \
sim:/lab5/cntr_14bit_out \
sim:/lab5/ones \
sim:/lab5/tens \
sim:/lab5/hundreds \
sim:/lab5/thousands \
sim:/lab5/digit_mux_out \
sim:/lab5/debounce_cnt \
sim:/lab5/digit_cnt \
sim:/lab5/rom_addr \
sim:/lab5/phase_accum_adder \
sim:/lab5/clean_enc_a \
sim:/lab5/clean_enc_b \
sim:/lab5/digit_clk \
sim:/lab5/pwm_clk \
sim:/lab5/clk_4khz \
sim:/lab5/clk_16mhz \
sim:/lab5/debounce_clk \
sim:/lab5/reset \
sim:/lab5/digit_seq_ns \
sim:/lab5/digit_seq_ps
run 200
# ** Warning: (vsim-8315) lab5.sv(147): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 1  Instance: /lab5
do do.do
run 10 us
run 1ms
run 10 ms
do do.do
restart -f
do do.do
# ** Warning: (vsim-8315) lab5.sv(147): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ns  Iteration: 1  Instance: /lab5
vsim -t ps lab5
# End time: 14:36:10 on May 05,2016, Elapsed time: 0:06:08
# Errors: 0, Warnings: 8
# vsim -t ps lab5 
# Start time: 14:36:10 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
add wave -position insertpoint  \
sim:/lab5/encoder_a \
sim:/lab5/encoder_b \
sim:/lab5/segment_data \
sim:/lab5/sel0 \
sim:/lab5/sel1 \
sim:/lab5/sel2 \
sim:/lab5/enable3to8 \
sim:/lab5/enable3to8_n \
sim:/lab5/pwm_output \
sim:/lab5/rom_data \
sim:/lab5/reset_n \
sim:/lab5/logic_one \
sim:/lab5/bcd_cnt_enable \
sim:/lab5/up_d_n \
sim:/lab5/cntr_14bit_out \
sim:/lab5/ones \
sim:/lab5/tens \
sim:/lab5/hundreds \
sim:/lab5/thousands \
sim:/lab5/digit_mux_out \
sim:/lab5/debounce_cnt \
sim:/lab5/digit_cnt \
sim:/lab5/rom_addr \
sim:/lab5/phase_accum_adder \
sim:/lab5/clean_enc_a \
sim:/lab5/clean_enc_b \
sim:/lab5/digit_clk \
sim:/lab5/pwm_clk \
sim:/lab5/clk_4khz \
sim:/lab5/clk_16mhz \
sim:/lab5/debounce_clk \
sim:/lab5/reset \
sim:/lab5/digit_seq_ns \
sim:/lab5/digit_seq_ps
do do.do
# ** Warning: (vsim-8315) lab5.sv(147): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(130): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 1  Instance: /lab5
run 10 ms
force encoder_b 1
run 6 ms
run 5 ms
force encoder_a 0
run 6 ms
force encoder_b 0
run 10 ms
!vlog
# vlog *.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 14:49:52 on May 05,2016
# vlog -reportprogress 300 bcd2_7seg.sv bcd_updn.sv bin2bcd.sv cntr_updn_14bit.sv debouncer.sv lab5.sv quad_decode.sv sine_rom.sv 
# -- Compiling module bcd2_7seg
# -- Compiling module bcd_updn
# -- Compiling module bin2bcd
# -- Compiling module cntr_updn_14bit
# -- Compiling module debouncer
# -- Compiling module lab5
# ** Error: (vlog-13069) lab5.sv(31): near "logic": syntax error, unexpected logic, expecting ';' or ','.
# ** Error: lab5.sv(92): (vlog-2730) Undefined variable: 'rom_addr'.
# -- Compiling module quad_decode
# -- Compiling module sine_rom
# End time: 14:49:52 on May 05,2016, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# /home/traylor/altera_lite/15.1/modelsim_ase/linuxaloem/vlog failed.
!vlog
# vlog *.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 14:50:19 on May 05,2016
# vlog -reportprogress 300 bcd2_7seg.sv bcd_updn.sv bin2bcd.sv cntr_updn_14bit.sv debouncer.sv lab5.sv quad_decode.sv sine_rom.sv 
# -- Compiling module bcd2_7seg
# -- Compiling module bcd_updn
# -- Compiling module bin2bcd
# -- Compiling module cntr_updn_14bit
# -- Compiling module debouncer
# -- Compiling module lab5
# -- Compiling module quad_decode
# -- Compiling module sine_rom
# 
# Top level modules:
# 	bcd_updn
# 	lab5
# End time: 14:50:19 on May 05,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim lab5.sv
# OpenFile lab5.sv
!vlog
# vlog *.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 14:50:36 on May 05,2016
# vlog -reportprogress 300 bcd2_7seg.sv bcd_updn.sv bin2bcd.sv cntr_updn_14bit.sv debouncer.sv lab5.sv quad_decode.sv sine_rom.sv 
# -- Compiling module bcd2_7seg
# -- Compiling module bcd_updn
# -- Compiling module bin2bcd
# -- Compiling module cntr_updn_14bit
# -- Compiling module debouncer
# -- Compiling module lab5
# -- Compiling module quad_decode
# -- Compiling module sine_rom
# 
# Top level modules:
# 	bcd_updn
# 	lab5
# End time: 14:50:36 on May 05,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim lab5
# End time: 14:50:42 on May 05,2016, Elapsed time: 0:14:32
# Errors: 3, Warnings: 4
# vsim lab5 
# Start time: 14:50:42 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
add wave -position insertpoint  \
sim:/lab5/PWM_CYCLE \
sim:/lab5/FOUR_KHZ_CYCLE \
sim:/lab5/CLK16MHZCYCLE \
sim:/lab5/inclk0_sig \
sim:/lab5/encoder_a \
sim:/lab5/encoder_b \
sim:/lab5/segment_data \
sim:/lab5/sel0 \
sim:/lab5/sel1 \
sim:/lab5/sel2 \
sim:/lab5/enable3to8 \
sim:/lab5/enable3to8_n \
sim:/lab5/pwm_output \
sim:/lab5/rom_data \
sim:/lab5/reset_n \
sim:/lab5/logic_one \
sim:/lab5/bcd_cnt_enable \
sim:/lab5/up_d_n \
sim:/lab5/cntr_14bit_out \
sim:/lab5/ones \
sim:/lab5/tens \
sim:/lab5/hundreds \
sim:/lab5/thousands \
sim:/lab5/digit_mux_out \
sim:/lab5/debounce_cnt \
sim:/lab5/digit_cnt \
sim:/lab5/rom_addr_strict \
sim:/lab5/rom_addr \
sim:/lab5/phase_accum_adder \
sim:/lab5/clean_enc_a \
sim:/lab5/clean_enc_b \
sim:/lab5/digit_clk \
sim:/lab5/pwm_clk \
sim:/lab5/clk_4khz \
sim:/lab5/clk_16mhz \
sim:/lab5/debounce_clk \
sim:/lab5/reset \
sim:/lab5/digit_seq_ns \
sim:/lab5/digit_seq_ps
do do.do
# ** Warning: (vsim-8315) lab5.sv(150): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 1  Instance: /lab5

run 10 ms
!vlog
# vlog *.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 14:55:16 on May 05,2016
# vlog -reportprogress 300 bcd2_7seg.sv bcd_updn.sv bin2bcd.sv cntr_updn_14bit.sv debouncer.sv lab5.sv quad_decode.sv sine_rom.sv 
# -- Compiling module bcd2_7seg
# -- Compiling module bcd_updn
# -- Compiling module bin2bcd
# -- Compiling module cntr_updn_14bit
# -- Compiling module debouncer
# -- Compiling module lab5
# -- Compiling module quad_decode
# -- Compiling module sine_rom
# 
# Top level modules:
# 	bcd_updn
# 	lab5
# End time: 14:55:16 on May 05,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim lab5
# End time: 14:55:23 on May 05,2016, Elapsed time: 0:04:41
# Errors: 0, Warnings: 4
# vsim lab5 
# Start time: 14:55:23 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
# ** Warning: (vsim-3015) lab5.sv(90): [PCDPC] - Port size (11) does not match connection size (10) for port 'addr'. The port definition is at: sine_rom.sv(4).
#    Time: 0 ps  Iteration: 0  Instance: /lab5/sine_rom_0 File: sine_rom.sv
do do.do
# ** Warning: (vsim-8315) lab5.sv(150): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 1  Instance: /lab5
!vlog
# vlog *.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 16:12:23 on May 05,2016
# vlog -reportprogress 300 bcd2_7seg.sv bcd_updn.sv bin2bcd.sv cntr_updn_14bit.sv debouncer.sv lab5.sv quad_decode.sv sine_rom.sv 
# -- Compiling module bcd2_7seg
# -- Compiling module bcd_updn
# -- Compiling module bin2bcd
# -- Compiling module cntr_updn_14bit
# -- Compiling module debouncer
# -- Compiling module lab5
# -- Compiling module quad_decode
# -- Compiling module sine_rom
# 
# Top level modules:
# 	bcd_updn
# 	lab5
# End time: 16:12:24 on May 05,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
vsim lab5
# End time: 16:12:32 on May 05,2016, Elapsed time: 1:17:09
# Errors: 0, Warnings: 5
# vsim lab5 
# Start time: 16:12:32 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
# ** Warning: (vsim-3015) lab5.sv(90): [PCDPC] - Port size (11) does not match connection size (10) for port 'addr'. The port definition is at: sine_rom.sv(4).
#    Time: 0 ps  Iteration: 0  Instance: /lab5/sine_rom_0 File: sine_rom.sv
vlog lab5.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 16:19:02 on May 05,2016
# vlog -reportprogress 300 lab5.sv 
# -- Compiling module lab5
# 
# Top level modules:
# 	lab5
# End time: 16:19:02 on May 05,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim lab5
# End time: 16:19:12 on May 05,2016, Elapsed time: 0:06:40
# Errors: 0, Warnings: 1
# vsim lab5 
# Start time: 16:19:12 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
vlog lab5.sv
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 16:19:22 on May 05,2016
# vlog -reportprogress 300 lab5.sv 
# -- Compiling module lab5
# 
# Top level modules:
# 	lab5
# End time: 16:19:22 on May 05,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim lab5
# End time: 16:19:25 on May 05,2016, Elapsed time: 0:00:13
# Errors: 0, Warnings: 0
# vsim lab5 
# Start time: 16:19:25 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
add wave -position insertpoint  \
sim:/lab5/encoder_a \
sim:/lab5/encoder_b \
sim:/lab5/segment_data \
sim:/lab5/sel0 \
sim:/lab5/sel1 \
sim:/lab5/sel2 \
sim:/lab5/enable3to8 \
sim:/lab5/enable3to8_n \
sim:/lab5/pwm_output \
sim:/lab5/rom_data \
sim:/lab5/reset_n \
sim:/lab5/logic_one \
sim:/lab5/bcd_cnt_enable \
sim:/lab5/up_d_n \
sim:/lab5/cntr_14bit_out \
sim:/lab5/ones \
sim:/lab5/tens \
sim:/lab5/hundreds \
sim:/lab5/thousands \
sim:/lab5/digit_mux_out \
sim:/lab5/debounce_cnt \
sim:/lab5/digit_cnt \
sim:/lab5/rom_addr_strict \
sim:/lab5/rom_addr \
sim:/lab5/phase_accum_adder \
sim:/lab5/clean_enc_a \
sim:/lab5/clean_enc_b \
sim:/lab5/digit_clk \
sim:/lab5/pwm_clk \
sim:/lab5/clk_4khz \
sim:/lab5/clk_16mhz \
sim:/lab5/debounce_clk \
sim:/lab5/reset \
sim:/lab5/digit_seq_ns \
sim:/lab5/digit_seq_ps
run 1 ms
# ** Warning: (vsim-8315) lab5.sv(150): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 1  Instance: /lab5
do do.do
run 5 ms
add wave -position insertpoint  \
sim:/lab5/rom_data
run 20 ms
run 200 ms
run 500 ms
!vsim
# vsim lab5
# End time: 16:30:11 on May 05,2016, Elapsed time: 0:10:46
# Errors: 0, Warnings: 4
# vsim lab5 
# Start time: 16:30:11 on May 05,2016
# Loading sv_std.std
# Loading work.lab5
# Loading work.debouncer
# Loading work.quad_decode
# Loading work.sine_rom
# Loading work.cntr_updn_14bit
# Loading work.bin2bcd
# Loading work.bcd2_7seg
do do.do
# ** Warning: (vsim-8315) lab5.sv(150): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5
# ** Warning: (vsim-8315) bcd2_7seg.sv(11): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 0  Instance: /lab5/bcd2_7seg_0
# ** Warning: (vsim-8315) lab5.sv(133): No condition is true in the unique/priority if/case statement.
#    Time: 0 ps  Iteration: 1  Instance: /lab5
run 5 ms
quit
# End time: 16:32:43 on May 05,2016, Elapsed time: 0:02:32
# Errors: 0, Warnings: 4