# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
# Date created = 17:40:03  March 30, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		sev_seg_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY sev_seg
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:40:03  MARCH 30, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro"
set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_B5 -to buttons[7]
set_location_assignment PIN_A4 -to buttons[6]
set_location_assignment PIN_D3 -to buttons[0]
set_location_assignment PIN_B4 -to buttons[5]
set_location_assignment PIN_B3 -to buttons[4]
set_location_assignment PIN_A3 -to buttons[3]
set_location_assignment PIN_A2 -to buttons[2]
set_location_assignment PIN_C3 -to buttons[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to buttons[6]
set_location_assignment PIN_R8 -to clk


set_global_assignment -name SYSTEMVERILOG_FILE ../src/sev_seg.sv
set_global_assignment -name QIP_FILE pll_leds.qip
set_location_assignment PIN_E9 -to pwm
set_location_assignment PIN_B7 -to reset
set_location_assignment PIN_E11 -to LEDs[0]
set_location_assignment PIN_D12 -to LEDs[6]
set_location_assignment PIN_D11 -to LEDs[5]
set_location_assignment PIN_A12 -to LEDs[4]
set_location_assignment PIN_B11 -to LEDs[3]
set_location_assignment PIN_C11 -to LEDs[2]
set_location_assignment PIN_E10 -to LEDs[1]
set_location_assignment PIN_F9 -to sel[2]
set_location_assignment PIN_F8 -to sel[1]
set_location_assignment PIN_E8 -to sel[0]
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name QIP_FILE test_pll.qip