Analysis & Synthesis report for lab6
Wed May 25 16:53:24 2016
Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis IP Cores Summary
  9. State Machine - |lab6|serial_bit_cntr_ps
 10. State Machine - |lab6|uart_main_ps
 11. State Machine - |lab6|button_pulse_ps
 12. State Machine - |lab6|uart_rcv:uart_rcv_0|bit_16x_cntr_ps
 13. State Machine - |lab6|uart_rcv:uart_rcv_0|rx_state_tracker_ps
 14. State Machine - |lab6|adc_control:adc_control_0|adc_ps
 15. Registers Removed During Synthesis
 16. General Register Statistics
 17. Inverted Register Statistics
 18. Multiplexer Restructuring Statistics (Restructuring Performed)
 19. Parameter Settings for User Entity Instance: Top-level Entity: |lab6
 20. Parameter Settings for User Entity Instance: lab6_pll1:lab6_pll1_inst|altpll:altpll_component
 21. Parameter Settings for User Entity Instance: lab6_pll2:lab6_pll2_inst|altpll:altpll_component
 22. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0
 23. Parameter Settings for Inferred Entity Instance: lpm_divide:Div0
 24. altpll Parameter Settings by Entity Instance
 25. lpm_mult Parameter Settings by Entity Instance
 26. Port Connectivity Checks: "uart_rcv:uart_rcv_0"
 27. Post-Synthesis Netlist Statistics for Top Partition
 28. Elapsed Time Per Partition
 29. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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that your use is for the sole purpose of programming logic 
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agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed May 25 16:53:24 2016       ;
; Quartus Prime Version              ; 15.1.1 Build 189 12/02/2015 SJ Lite Edition ;
; Revision Name                      ; lab6                                        ;
; Top-level Entity Name              ; lab6                                        ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 665                                         ;
;     Total combinational functions  ; 615                                         ;
;     Dedicated logic registers      ; 95                                          ;
; Total registers                    ; 95                                          ;
; Total pins                         ; 22                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 2                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22F17C6       ;                    ;
; Top-level entity name                                                      ; lab6               ; lab6               ;
; Family name                                                                ; Cyclone IV E       ; Cyclone V          ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                           ; Library ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------+---------+
; lab6.sv                          ; yes             ; User SystemVerilog HDL File        ; /home/traylor/fpga/lab6/lab6.sv                                                        ;         ;
; bcd2_7seg.sv                     ; yes             ; User SystemVerilog HDL File        ; /home/traylor/fpga/lab6/bcd2_7seg.sv                                                   ;         ;
; bin2bcd.sv                       ; yes             ; User SystemVerilog HDL File        ; /home/traylor/fpga/lab6/bin2bcd.sv                                                     ;         ;
; adc_control.sv                   ; yes             ; User SystemVerilog HDL File        ; /home/traylor/fpga/lab6/adc_control.sv                                                 ;         ;
; lab6_pll1.v                      ; yes             ; User Wizard-Generated File         ; /home/traylor/fpga/lab6/lab6_pll1.v                                                    ;         ;
; lab6_pll2.v                      ; yes             ; User Wizard-Generated File         ; /home/traylor/fpga/lab6/lab6_pll2.v                                                    ;         ;
; uart_rcv.sv                      ; yes             ; Auto-Found SystemVerilog HDL File  ; /home/traylor/fpga/lab6/uart_rcv.sv                                                    ;         ;
; altpll.tdf                       ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf              ;         ;
; aglobal151.inc                   ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/aglobal151.inc          ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratix_pll.inc         ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/stratixii_pll.inc       ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/cycloneii_pll.inc       ;         ;
; db/lab6_pll1_altpll1.v           ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/lab6_pll1_altpll1.v                                         ;         ;
; db/lab6_pll2_altpll.v            ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/lab6_pll2_altpll.v                                          ;         ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_mult.tdf            ;         ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_add_sub.inc         ;         ;
; multcore.inc                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/multcore.inc            ;         ;
; bypassff.inc                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/bypassff.inc            ;         ;
; altshift.inc                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altshift.inc            ;         ;
; multcore.tdf                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/multcore.tdf            ;         ;
; csa_add.inc                      ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/csa_add.inc             ;         ;
; mpar_add.inc                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mpar_add.inc            ;         ;
; muleabz.inc                      ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/muleabz.inc             ;         ;
; mul_lfrg.inc                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mul_lfrg.inc            ;         ;
; mul_boothc.inc                   ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mul_boothc.inc          ;         ;
; alt_ded_mult.inc                 ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/alt_ded_mult.inc        ;         ;
; alt_ded_mult_y.inc               ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/alt_ded_mult_y.inc      ;         ;
; dffpipe.inc                      ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/dffpipe.inc             ;         ;
; mpar_add.tdf                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mpar_add.tdf            ;         ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;         ;
; addcore.inc                      ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/addcore.inc             ;         ;
; look_add.inc                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/look_add.inc            ;         ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;         ;
; db/add_sub_ngh.tdf               ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/add_sub_ngh.tdf                                             ;         ;
; db/add_sub_rgh.tdf               ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/add_sub_rgh.tdf                                             ;         ;
; altshift.tdf                     ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altshift.tdf            ;         ;
; lpm_divide.tdf                   ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_divide.tdf          ;         ;
; abs_divider.inc                  ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/abs_divider.inc         ;         ;
; sign_div_unsign.inc              ; yes             ; Megafunction                       ; /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/sign_div_unsign.inc     ;         ;
; db/lpm_divide_dkm.tdf            ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/lpm_divide_dkm.tdf                                          ;         ;
; db/sign_div_unsign_5nh.tdf       ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/sign_div_unsign_5nh.tdf                                     ;         ;
; db/alt_u_div_u9f.tdf             ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/alt_u_div_u9f.tdf                                           ;         ;
; db/add_sub_7pc.tdf               ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/add_sub_7pc.tdf                                             ;         ;
; db/add_sub_8pc.tdf               ; yes             ; Auto-Generated Megafunction        ; /home/traylor/fpga/lab6/db/add_sub_8pc.tdf                                             ;         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Estimated Total logic elements              ; 665           ;
;                                             ;               ;
; Total combinational functions               ; 615           ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 231           ;
;     -- 3 input functions                    ; 162           ;
;     -- <=2 input functions                  ; 222           ;
;                                             ;               ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 448           ;
;     -- arithmetic mode                      ; 167           ;
;                                             ;               ;
; Total registers                             ; 95            ;
;     -- Dedicated logic registers            ; 95            ;
;     -- I/O registers                        ; 0             ;
;                                             ;               ;
; I/O pins                                    ; 22            ;
;                                             ;               ;
; Embedded Multiplier 9-bit elements          ; 0             ;
;                                             ;               ;
; Total PLLs                                  ; 2             ;
;     -- PLLs                                 ; 2             ;
;                                             ;               ;
; Maximum fan-out node                        ; reset_n~input ;
; Maximum fan-out                             ; 97            ;
; Total fan-out                               ; 2198          ;
; Average fan-out                             ; 2.91          ;
+---------------------------------------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                      ;
+------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                     ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                          ; Library Name ;
+------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------+--------------+
; |lab6                                          ; 615 (68)          ; 95 (52)      ; 0           ; 0            ; 0       ; 0         ; 22   ; 0            ; |lab6                                                                                                                        ; work         ;
;    |adc_control:adc_control_0|                 ; 14 (14)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|adc_control:adc_control_0                                                                                              ; work         ;
;    |bcd2_7seg:bcd2_7seg_0|                     ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|bcd2_7seg:bcd2_7seg_0                                                                                                  ; work         ;
;    |bin2bcd:bin2bcd_0|                         ; 71 (71)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|bin2bcd:bin2bcd_0                                                                                                      ; work         ;
;    |lab6_pll1:lab6_pll1_inst|                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lab6_pll1:lab6_pll1_inst                                                                                               ; work         ;
;       |altpll:altpll_component|                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lab6_pll1:lab6_pll1_inst|altpll:altpll_component                                                                       ; work         ;
;          |lab6_pll1_altpll1:auto_generated|    ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lab6_pll1:lab6_pll1_inst|altpll:altpll_component|lab6_pll1_altpll1:auto_generated                                      ; work         ;
;    |lab6_pll2:lab6_pll2_inst|                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lab6_pll2:lab6_pll2_inst                                                                                               ; work         ;
;       |altpll:altpll_component|                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lab6_pll2:lab6_pll2_inst|altpll:altpll_component                                                                       ; work         ;
;          |lab6_pll2_altpll:auto_generated|     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lab6_pll2:lab6_pll2_inst|altpll:altpll_component|lab6_pll2_altpll:auto_generated                                       ; work         ;
;    |lpm_divide:Div0|                           ; 390 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_divide:Div0                                                                                                        ; work         ;
;       |lpm_divide_dkm:auto_generated|          ; 390 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_divide:Div0|lpm_divide_dkm:auto_generated                                                                          ; work         ;
;          |sign_div_unsign_5nh:divider|         ; 390 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_divide:Div0|lpm_divide_dkm:auto_generated|sign_div_unsign_5nh:divider                                              ; work         ;
;             |alt_u_div_u9f:divider|            ; 390 (390)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_divide:Div0|lpm_divide_dkm:auto_generated|sign_div_unsign_5nh:divider|alt_u_div_u9f:divider                        ; work         ;
;    |lpm_mult:Mult0|                            ; 49 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0                                                                                                         ; work         ;
;       |multcore:mult_core|                     ; 49 (27)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core                                                                                      ; work         ;
;          |mpar_add:padder|                     ; 22 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder                                                                      ; work         ;
;             |lpm_add_sub:adder[0]|             ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; work         ;
;                |add_sub_ngh:auto_generated|    ; 11 (11)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_ngh:auto_generated                      ; work         ;
;             |mpar_add:sub_par_add|             ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; work         ;
;                |lpm_add_sub:adder[0]|          ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; work         ;
;                   |add_sub_rgh:auto_generated| ; 11 (11)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_rgh:auto_generated ; work         ;
;    |uart_rcv:uart_rcv_0|                       ; 16 (16)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lab6|uart_rcv:uart_rcv_0                                                                                                    ; work         ;
+------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                            ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                ; IP Include File ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
; Altera ; ALTPLL       ; 15.1    ; N/A          ; N/A          ; |lab6|lab6_pll1:lab6_pll1_inst ; lab6_pll1.v     ;
; Altera ; ALTPLL       ; 15.1    ; N/A          ; N/A          ; |lab6|lab6_pll2:lab6_pll2_inst ; lab6_pll2.v     ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lab6|serial_bit_cntr_ps                                                                                                                                                                                                                                                               ;
+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+
; Name                     ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_9 ;
+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+
; serial_bit_cntr_ps.BIT_9 ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ;
; serial_bit_cntr_ps.BIT_1 ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ; 1                        ;
; serial_bit_cntr_ps.BIT_2 ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_3 ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ; 0                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_4 ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ; 0                        ; 0                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_5 ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_6 ; 0                        ; 0                        ; 0                        ; 1                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_7 ; 0                        ; 0                        ; 1                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_8 ; 0                        ; 1                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ;
; serial_bit_cntr_ps.BIT_0 ; 1                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 0                        ; 1                        ;
+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lab6|uart_main_ps                                                                                                                                            ;
+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+
; Name                ; uart_main_ps.CHAR_0 ; uart_main_ps.CHAR_5 ; uart_main_ps.CHAR_4 ; uart_main_ps.CHAR_3 ; uart_main_ps.CHAR_2 ; uart_main_ps.CHAR_1 ; uart_main_ps.CHAR_6 ;
+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+
; uart_main_ps.CHAR_6 ; 0                   ; 0                   ; 0                   ; 0                   ; 0                   ; 0                   ; 0                   ;
; uart_main_ps.CHAR_1 ; 0                   ; 0                   ; 0                   ; 0                   ; 0                   ; 1                   ; 1                   ;
; uart_main_ps.CHAR_2 ; 0                   ; 0                   ; 0                   ; 0                   ; 1                   ; 0                   ; 1                   ;
; uart_main_ps.CHAR_3 ; 0                   ; 0                   ; 0                   ; 1                   ; 0                   ; 0                   ; 1                   ;
; uart_main_ps.CHAR_4 ; 0                   ; 0                   ; 1                   ; 0                   ; 0                   ; 0                   ; 1                   ;
; uart_main_ps.CHAR_5 ; 0                   ; 1                   ; 0                   ; 0                   ; 0                   ; 0                   ; 1                   ;
; uart_main_ps.CHAR_0 ; 1                   ; 0                   ; 0                   ; 0                   ; 0                   ; 0                   ; 1                   ;
+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+---------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------+
; State Machine - |lab6|button_pulse_ps                                                          ;
+------------------------+------------------------+-----------------------+----------------------+
; Name                   ; button_pulse_ps.DETECT ; button_pulse_ps.PULSE ; button_pulse_ps.WAIT ;
+------------------------+------------------------+-----------------------+----------------------+
; button_pulse_ps.DETECT ; 0                      ; 0                     ; 0                    ;
; button_pulse_ps.WAIT   ; 1                      ; 0                     ; 1                    ;
; button_pulse_ps.PULSE  ; 1                      ; 1                     ; 0                    ;
+------------------------+------------------------+-----------------------+----------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lab6|uart_rcv:uart_rcv_0|bit_16x_cntr_ps                                                                                                                                                                                                                                                                                                                                                                    ;
+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+
; Name                   ; bit_16x_cntr_ps.BIT_15 ; bit_16x_cntr_ps.BIT_14 ; bit_16x_cntr_ps.BIT_13 ; bit_16x_cntr_ps.BIT_12 ; bit_16x_cntr_ps.BIT_11 ; bit_16x_cntr_ps.BIT_10 ; bit_16x_cntr_ps.BIT_0 ; bit_16x_cntr_ps.BIT_8 ; bit_16x_cntr_ps.BIT_7 ; bit_16x_cntr_ps.BIT_6 ; bit_16x_cntr_ps.BIT_5 ; bit_16x_cntr_ps.BIT_4 ; bit_16x_cntr_ps.BIT_3 ; bit_16x_cntr_ps.BIT_2 ; bit_16x_cntr_ps.BIT_1 ; bit_16x_cntr_ps.BIT_9 ;
+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+
; bit_16x_cntr_ps.BIT_9  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ;
; bit_16x_cntr_ps.BIT_1  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ; 1                     ;
; bit_16x_cntr_ps.BIT_2  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_3  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_4  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_5  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_6  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 1                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_7  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 1                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_8  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 1                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_0  ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 1                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_10 ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 1                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_11 ; 0                      ; 0                      ; 0                      ; 0                      ; 1                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_12 ; 0                      ; 0                      ; 0                      ; 1                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_13 ; 0                      ; 0                      ; 1                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_14 ; 0                      ; 1                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
; bit_16x_cntr_ps.BIT_15 ; 1                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                      ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 0                     ; 1                     ;
+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lab6|uart_rcv:uart_rcv_0|rx_state_tracker_ps                                                                                                                 ;
+-------------------------------------+------------------------------+-------------------------------------+-----------------------------------+--------------------------------+
; Name                                ; rx_state_tracker_ps.STOP_BIT ; rx_state_tracker_ps.START_VALIDATED ; rx_state_tracker_ps.EDGE_DETECTED ; rx_state_tracker_ps.NOT_DETECT ;
+-------------------------------------+------------------------------+-------------------------------------+-----------------------------------+--------------------------------+
; rx_state_tracker_ps.NOT_DETECT      ; 0                            ; 0                                   ; 0                                 ; 0                              ;
; rx_state_tracker_ps.EDGE_DETECTED   ; 0                            ; 0                                   ; 1                                 ; 1                              ;
; rx_state_tracker_ps.START_VALIDATED ; 0                            ; 1                                   ; 0                                 ; 1                              ;
; rx_state_tracker_ps.STOP_BIT        ; 1                            ; 0                                   ; 0                                 ; 1                              ;
+-------------------------------------+------------------------------+-------------------------------------+-----------------------------------+--------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------+
; State Machine - |lab6|adc_control:adc_control_0|adc_ps  ;
+--------------+--------------+-------------+-------------+
; Name         ; adc_ps.START ; adc_ps.STOP ; adc_ps.IDLE ;
+--------------+--------------+-------------+-------------+
; adc_ps.IDLE  ; 0            ; 0           ; 0           ;
; adc_ps.START ; 1            ; 0           ; 1           ;
; adc_ps.STOP  ; 0            ; 1           ; 1           ;
+--------------+--------------+-------------+-------------+


+----------------------------------------------------------------+
; Registers Removed During Synthesis                             ;
+-------------------------------------------+--------------------+
; Register name                             ; Reason for Removal ;
+-------------------------------------------+--------------------+
; serial_bit_cntr_ps~4                      ; Lost fanout        ;
; serial_bit_cntr_ps~5                      ; Lost fanout        ;
; serial_bit_cntr_ps~6                      ; Lost fanout        ;
; serial_bit_cntr_ps~7                      ; Lost fanout        ;
; uart_main_ps~11                           ; Lost fanout        ;
; uart_main_ps~12                           ; Lost fanout        ;
; uart_main_ps~13                           ; Lost fanout        ;
; uart_rcv:uart_rcv_0|bit_16x_cntr_ps~4     ; Lost fanout        ;
; uart_rcv:uart_rcv_0|bit_16x_cntr_ps~5     ; Lost fanout        ;
; uart_rcv:uart_rcv_0|bit_16x_cntr_ps~6     ; Lost fanout        ;
; uart_rcv:uart_rcv_0|bit_16x_cntr_ps~7     ; Lost fanout        ;
; uart_rcv:uart_rcv_0|rx_state_tracker_ps~4 ; Lost fanout        ;
; uart_rcv:uart_rcv_0|rx_state_tracker_ps~5 ; Lost fanout        ;
; button_pulse_ps.WAIT                      ; Lost fanout        ;
; Total Number of Removed Registers = 14    ;                    ;
+-------------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 95    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 95    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 53    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; adc_control:adc_control_0|bit_count[0] ; 6       ;
; adc_control:adc_control_0|bit_count[1] ; 5       ;
; adc_control:adc_control_0|bit_count[2] ; 6       ;
; adc_control:adc_control_0|bit_count[3] ; 5       ;
; uart_rcv:uart_rcv_0|sync_data          ; 6       ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |lab6|Selector9            ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |lab6|Selector1            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |lab6 ;
+----------------+----------+------------------------------------------+
; Parameter Name ; Value    ; Type                                     ;
+----------------+----------+------------------------------------------+
; DP             ; 00101110 ; Unsigned Binary                          ;
; CR             ; 00001101 ; Unsigned Binary                          ;
; LF             ; 00001010 ; Unsigned Binary                          ;
; select_ASCII   ; 00       ; Unsigned Binary                          ;
; select_DP      ; 01       ; Unsigned Binary                          ;
; select_CR      ; 10       ; Unsigned Binary                          ;
; select_LF      ; 11       ; Unsigned Binary                          ;
; DIGIT_1000s    ; 11       ; Unsigned Binary                          ;
; DIGIT_100s     ; 10       ; Unsigned Binary                          ;
; DIGIT_10s      ; 01       ; Unsigned Binary                          ;
; DIGIT_1s       ; 00       ; Unsigned Binary                          ;
+----------------+----------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lab6_pll1:lab6_pll1_inst|altpll:altpll_component ;
+-------------------------------+-----------------------------+---------------------------------+
; Parameter Name                ; Value                       ; Type                            ;
+-------------------------------+-----------------------------+---------------------------------+
; OPERATION_MODE                ; NORMAL                      ; Untyped                         ;
; PLL_TYPE                      ; AUTO                        ; Untyped                         ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=lab6_pll1 ; Untyped                         ;
; QUALIFY_CONF_DONE             ; OFF                         ; Untyped                         ;
; COMPENSATE_CLOCK              ; CLK0                        ; Untyped                         ;
; SCAN_CHAIN                    ; LONG                        ; Untyped                         ;
; PRIMARY_CLOCK                 ; INCLK0                      ; Untyped                         ;
; INCLK0_INPUT_FREQUENCY        ; 20000                       ; Signed Integer                  ;
; INCLK1_INPUT_FREQUENCY        ; 0                           ; Untyped                         ;
; GATE_LOCK_SIGNAL              ; NO                          ; Untyped                         ;
; GATE_LOCK_COUNTER             ; 0                           ; Untyped                         ;
; LOCK_HIGH                     ; 1                           ; Untyped                         ;
; LOCK_LOW                      ; 1                           ; Untyped                         ;
; VALID_LOCK_MULTIPLIER         ; 1                           ; Untyped                         ;
; INVALID_LOCK_MULTIPLIER       ; 5                           ; Untyped                         ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                         ; Untyped                         ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                         ; Untyped                         ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                         ; Untyped                         ;
; SKIP_VCO                      ; OFF                         ; Untyped                         ;
; SWITCH_OVER_COUNTER           ; 0                           ; Untyped                         ;
; SWITCH_OVER_TYPE              ; AUTO                        ; Untyped                         ;
; FEEDBACK_SOURCE               ; EXTCLK0                     ; Untyped                         ;
; BANDWIDTH                     ; 0                           ; Untyped                         ;
; BANDWIDTH_TYPE                ; AUTO                        ; Untyped                         ;
; SPREAD_FREQUENCY              ; 0                           ; Untyped                         ;
; DOWN_SPREAD                   ; 0                           ; Untyped                         ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                         ; Untyped                         ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                         ; Untyped                         ;
; CLK9_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK8_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK7_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK6_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK5_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK4_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK3_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK2_MULTIPLY_BY              ; 48                          ; Signed Integer                  ;
; CLK1_MULTIPLY_BY              ; 1                           ; Signed Integer                  ;
; CLK0_MULTIPLY_BY              ; 3                           ; Signed Integer                  ;
; CLK9_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK8_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK7_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK6_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK5_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK4_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK3_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK2_DIVIDE_BY                ; 15625                       ; Signed Integer                  ;
; CLK1_DIVIDE_BY                ; 12500                       ; Signed Integer                  ;
; CLK0_DIVIDE_BY                ; 50                          ; Signed Integer                  ;
; CLK9_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK8_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK7_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK6_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK5_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK4_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK3_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK2_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK1_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK0_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK5_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK4_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK3_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK2_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK1_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK0_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK9_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK8_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK7_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK6_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK5_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK4_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK3_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK2_DUTY_CYCLE               ; 50                          ; Signed Integer                  ;
; CLK1_DUTY_CYCLE               ; 50                          ; Signed Integer                  ;
; CLK0_DUTY_CYCLE               ; 50                          ; Signed Integer                  ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; LOCK_WINDOW_UI                ;  0.05                       ; Untyped                         ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                      ; Untyped                         ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                      ; Untyped                         ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                      ; Untyped                         ;
; DPA_MULTIPLY_BY               ; 0                           ; Untyped                         ;
; DPA_DIVIDE_BY                 ; 1                           ; Untyped                         ;
; DPA_DIVIDER                   ; 0                           ; Untyped                         ;
; EXTCLK3_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK2_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK1_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK0_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK3_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK2_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK1_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK0_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK3_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK2_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK1_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK0_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK3_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK2_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK1_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK0_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK3_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; EXTCLK2_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; EXTCLK1_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; EXTCLK0_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; VCO_MULTIPLY_BY               ; 0                           ; Untyped                         ;
; VCO_DIVIDE_BY                 ; 0                           ; Untyped                         ;
; SCLKOUT0_PHASE_SHIFT          ; 0                           ; Untyped                         ;
; SCLKOUT1_PHASE_SHIFT          ; 0                           ; Untyped                         ;
; VCO_MIN                       ; 0                           ; Untyped                         ;
; VCO_MAX                       ; 0                           ; Untyped                         ;
; VCO_CENTER                    ; 0                           ; Untyped                         ;
; PFD_MIN                       ; 0                           ; Untyped                         ;
; PFD_MAX                       ; 0                           ; Untyped                         ;
; M_INITIAL                     ; 0                           ; Untyped                         ;
; M                             ; 0                           ; Untyped                         ;
; N                             ; 1                           ; Untyped                         ;
; M2                            ; 1                           ; Untyped                         ;
; N2                            ; 1                           ; Untyped                         ;
; SS                            ; 1                           ; Untyped                         ;
; C0_HIGH                       ; 0                           ; Untyped                         ;
; C1_HIGH                       ; 0                           ; Untyped                         ;
; C2_HIGH                       ; 0                           ; Untyped                         ;
; C3_HIGH                       ; 0                           ; Untyped                         ;
; C4_HIGH                       ; 0                           ; Untyped                         ;
; C5_HIGH                       ; 0                           ; Untyped                         ;
; C6_HIGH                       ; 0                           ; Untyped                         ;
; C7_HIGH                       ; 0                           ; Untyped                         ;
; C8_HIGH                       ; 0                           ; Untyped                         ;
; C9_HIGH                       ; 0                           ; Untyped                         ;
; C0_LOW                        ; 0                           ; Untyped                         ;
; C1_LOW                        ; 0                           ; Untyped                         ;
; C2_LOW                        ; 0                           ; Untyped                         ;
; C3_LOW                        ; 0                           ; Untyped                         ;
; C4_LOW                        ; 0                           ; Untyped                         ;
; C5_LOW                        ; 0                           ; Untyped                         ;
; C6_LOW                        ; 0                           ; Untyped                         ;
; C7_LOW                        ; 0                           ; Untyped                         ;
; C8_LOW                        ; 0                           ; Untyped                         ;
; C9_LOW                        ; 0                           ; Untyped                         ;
; C0_INITIAL                    ; 0                           ; Untyped                         ;
; C1_INITIAL                    ; 0                           ; Untyped                         ;
; C2_INITIAL                    ; 0                           ; Untyped                         ;
; C3_INITIAL                    ; 0                           ; Untyped                         ;
; C4_INITIAL                    ; 0                           ; Untyped                         ;
; C5_INITIAL                    ; 0                           ; Untyped                         ;
; C6_INITIAL                    ; 0                           ; Untyped                         ;
; C7_INITIAL                    ; 0                           ; Untyped                         ;
; C8_INITIAL                    ; 0                           ; Untyped                         ;
; C9_INITIAL                    ; 0                           ; Untyped                         ;
; C0_MODE                       ; BYPASS                      ; Untyped                         ;
; C1_MODE                       ; BYPASS                      ; Untyped                         ;
; C2_MODE                       ; BYPASS                      ; Untyped                         ;
; C3_MODE                       ; BYPASS                      ; Untyped                         ;
; C4_MODE                       ; BYPASS                      ; Untyped                         ;
; C5_MODE                       ; BYPASS                      ; Untyped                         ;
; C6_MODE                       ; BYPASS                      ; Untyped                         ;
; C7_MODE                       ; BYPASS                      ; Untyped                         ;
; C8_MODE                       ; BYPASS                      ; Untyped                         ;
; C9_MODE                       ; BYPASS                      ; Untyped                         ;
; C0_PH                         ; 0                           ; Untyped                         ;
; C1_PH                         ; 0                           ; Untyped                         ;
; C2_PH                         ; 0                           ; Untyped                         ;
; C3_PH                         ; 0                           ; Untyped                         ;
; C4_PH                         ; 0                           ; Untyped                         ;
; C5_PH                         ; 0                           ; Untyped                         ;
; C6_PH                         ; 0                           ; Untyped                         ;
; C7_PH                         ; 0                           ; Untyped                         ;
; C8_PH                         ; 0                           ; Untyped                         ;
; C9_PH                         ; 0                           ; Untyped                         ;
; L0_HIGH                       ; 1                           ; Untyped                         ;
; L1_HIGH                       ; 1                           ; Untyped                         ;
; G0_HIGH                       ; 1                           ; Untyped                         ;
; G1_HIGH                       ; 1                           ; Untyped                         ;
; G2_HIGH                       ; 1                           ; Untyped                         ;
; G3_HIGH                       ; 1                           ; Untyped                         ;
; E0_HIGH                       ; 1                           ; Untyped                         ;
; E1_HIGH                       ; 1                           ; Untyped                         ;
; E2_HIGH                       ; 1                           ; Untyped                         ;
; E3_HIGH                       ; 1                           ; Untyped                         ;
; L0_LOW                        ; 1                           ; Untyped                         ;
; L1_LOW                        ; 1                           ; Untyped                         ;
; G0_LOW                        ; 1                           ; Untyped                         ;
; G1_LOW                        ; 1                           ; Untyped                         ;
; G2_LOW                        ; 1                           ; Untyped                         ;
; G3_LOW                        ; 1                           ; Untyped                         ;
; E0_LOW                        ; 1                           ; Untyped                         ;
; E1_LOW                        ; 1                           ; Untyped                         ;
; E2_LOW                        ; 1                           ; Untyped                         ;
; E3_LOW                        ; 1                           ; Untyped                         ;
; L0_INITIAL                    ; 1                           ; Untyped                         ;
; L1_INITIAL                    ; 1                           ; Untyped                         ;
; G0_INITIAL                    ; 1                           ; Untyped                         ;
; G1_INITIAL                    ; 1                           ; Untyped                         ;
; G2_INITIAL                    ; 1                           ; Untyped                         ;
; G3_INITIAL                    ; 1                           ; Untyped                         ;
; E0_INITIAL                    ; 1                           ; Untyped                         ;
; E1_INITIAL                    ; 1                           ; Untyped                         ;
; E2_INITIAL                    ; 1                           ; Untyped                         ;
; E3_INITIAL                    ; 1                           ; Untyped                         ;
; L0_MODE                       ; BYPASS                      ; Untyped                         ;
; L1_MODE                       ; BYPASS                      ; Untyped                         ;
; G0_MODE                       ; BYPASS                      ; Untyped                         ;
; G1_MODE                       ; BYPASS                      ; Untyped                         ;
; G2_MODE                       ; BYPASS                      ; Untyped                         ;
; G3_MODE                       ; BYPASS                      ; Untyped                         ;
; E0_MODE                       ; BYPASS                      ; Untyped                         ;
; E1_MODE                       ; BYPASS                      ; Untyped                         ;
; E2_MODE                       ; BYPASS                      ; Untyped                         ;
; E3_MODE                       ; BYPASS                      ; Untyped                         ;
; L0_PH                         ; 0                           ; Untyped                         ;
; L1_PH                         ; 0                           ; Untyped                         ;
; G0_PH                         ; 0                           ; Untyped                         ;
; G1_PH                         ; 0                           ; Untyped                         ;
; G2_PH                         ; 0                           ; Untyped                         ;
; G3_PH                         ; 0                           ; Untyped                         ;
; E0_PH                         ; 0                           ; Untyped                         ;
; E1_PH                         ; 0                           ; Untyped                         ;
; E2_PH                         ; 0                           ; Untyped                         ;
; E3_PH                         ; 0                           ; Untyped                         ;
; M_PH                          ; 0                           ; Untyped                         ;
; C1_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C2_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C3_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C4_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C5_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C6_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C7_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C8_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C9_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; CLK0_COUNTER                  ; G0                          ; Untyped                         ;
; CLK1_COUNTER                  ; G0                          ; Untyped                         ;
; CLK2_COUNTER                  ; G0                          ; Untyped                         ;
; CLK3_COUNTER                  ; G0                          ; Untyped                         ;
; CLK4_COUNTER                  ; G0                          ; Untyped                         ;
; CLK5_COUNTER                  ; G0                          ; Untyped                         ;
; CLK6_COUNTER                  ; E0                          ; Untyped                         ;
; CLK7_COUNTER                  ; E1                          ; Untyped                         ;
; CLK8_COUNTER                  ; E2                          ; Untyped                         ;
; CLK9_COUNTER                  ; E3                          ; Untyped                         ;
; L0_TIME_DELAY                 ; 0                           ; Untyped                         ;
; L1_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G0_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G1_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G2_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G3_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E0_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E1_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E2_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E3_TIME_DELAY                 ; 0                           ; Untyped                         ;
; M_TIME_DELAY                  ; 0                           ; Untyped                         ;
; N_TIME_DELAY                  ; 0                           ; Untyped                         ;
; EXTCLK3_COUNTER               ; E3                          ; Untyped                         ;
; EXTCLK2_COUNTER               ; E2                          ; Untyped                         ;
; EXTCLK1_COUNTER               ; E1                          ; Untyped                         ;
; EXTCLK0_COUNTER               ; E0                          ; Untyped                         ;
; ENABLE0_COUNTER               ; L0                          ; Untyped                         ;
; ENABLE1_COUNTER               ; L0                          ; Untyped                         ;
; CHARGE_PUMP_CURRENT           ; 2                           ; Untyped                         ;
; LOOP_FILTER_R                 ;  1.000000                   ; Untyped                         ;
; LOOP_FILTER_C                 ; 5                           ; Untyped                         ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                        ; Untyped                         ;
; LOOP_FILTER_R_BITS            ; 9999                        ; Untyped                         ;
; LOOP_FILTER_C_BITS            ; 9999                        ; Untyped                         ;
; VCO_POST_SCALE                ; 0                           ; Untyped                         ;
; CLK2_OUTPUT_FREQUENCY         ; 0                           ; Untyped                         ;
; CLK1_OUTPUT_FREQUENCY         ; 0                           ; Untyped                         ;
; CLK0_OUTPUT_FREQUENCY         ; 0                           ; Untyped                         ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E                ; Untyped                         ;
; PORT_CLKENA0                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA1                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA2                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA3                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA4                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA5                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLK0                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLK1                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLK2                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLK3                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKBAD0                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKBAD1                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK0                     ; PORT_USED                   ; Untyped                         ;
; PORT_CLK1                     ; PORT_USED                   ; Untyped                         ;
; PORT_CLK2                     ; PORT_USED                   ; Untyped                         ;
; PORT_CLK3                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK4                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK5                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK6                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK7                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK8                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK9                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANDATA                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANDATAOUT              ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANDONE                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKLOSS                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_INCLK1                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_INCLK0                   ; PORT_USED                   ; Untyped                         ;
; PORT_FBIN                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PLLENA                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKSWITCH                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_ARESET                   ; PORT_USED                   ; Untyped                         ;
; PORT_PFDENA                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANCLK                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANACLR                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANREAD                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANWRITE                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_LOCKED                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED                 ; Untyped                         ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_PHASEDONE                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PHASESTEP                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANCLKENA               ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED                 ; Untyped                         ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY           ; Untyped                         ;
; M_TEST_SOURCE                 ; 5                           ; Untyped                         ;
; C0_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C1_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C2_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C3_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C4_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C5_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C6_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C7_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C8_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C9_TEST_SOURCE                ; 5                           ; Untyped                         ;
; CBXI_PARAMETER                ; lab6_pll1_altpll1           ; Untyped                         ;
; VCO_FREQUENCY_CONTROL         ; AUTO                        ; Untyped                         ;
; VCO_PHASE_SHIFT_STEP          ; 0                           ; Untyped                         ;
; WIDTH_CLOCK                   ; 5                           ; Signed Integer                  ;
; WIDTH_PHASECOUNTERSELECT      ; 4                           ; Untyped                         ;
; USING_FBMIMICBIDIR_PORT       ; OFF                         ; Untyped                         ;
; DEVICE_FAMILY                 ; Cyclone IV E                ; Untyped                         ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                      ; Untyped                         ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                         ; Untyped                         ;
; AUTO_CARRY_CHAINS             ; ON                          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS          ; OFF                         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS           ; ON                          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS        ; OFF                         ; IGNORE_CASCADE                  ;
+-------------------------------+-----------------------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lab6_pll2:lab6_pll2_inst|altpll:altpll_component ;
+-------------------------------+-----------------------------+---------------------------------+
; Parameter Name                ; Value                       ; Type                            ;
+-------------------------------+-----------------------------+---------------------------------+
; OPERATION_MODE                ; NORMAL                      ; Untyped                         ;
; PLL_TYPE                      ; AUTO                        ; Untyped                         ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=lab6_pll2 ; Untyped                         ;
; QUALIFY_CONF_DONE             ; OFF                         ; Untyped                         ;
; COMPENSATE_CLOCK              ; CLK0                        ; Untyped                         ;
; SCAN_CHAIN                    ; LONG                        ; Untyped                         ;
; PRIMARY_CLOCK                 ; INCLK0                      ; Untyped                         ;
; INCLK0_INPUT_FREQUENCY        ; 20000                       ; Signed Integer                  ;
; INCLK1_INPUT_FREQUENCY        ; 0                           ; Untyped                         ;
; GATE_LOCK_SIGNAL              ; NO                          ; Untyped                         ;
; GATE_LOCK_COUNTER             ; 0                           ; Untyped                         ;
; LOCK_HIGH                     ; 1                           ; Untyped                         ;
; LOCK_LOW                      ; 1                           ; Untyped                         ;
; VALID_LOCK_MULTIPLIER         ; 1                           ; Untyped                         ;
; INVALID_LOCK_MULTIPLIER       ; 5                           ; Untyped                         ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                         ; Untyped                         ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                         ; Untyped                         ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                         ; Untyped                         ;
; SKIP_VCO                      ; OFF                         ; Untyped                         ;
; SWITCH_OVER_COUNTER           ; 0                           ; Untyped                         ;
; SWITCH_OVER_TYPE              ; AUTO                        ; Untyped                         ;
; FEEDBACK_SOURCE               ; EXTCLK0                     ; Untyped                         ;
; BANDWIDTH                     ; 0                           ; Untyped                         ;
; BANDWIDTH_TYPE                ; AUTO                        ; Untyped                         ;
; SPREAD_FREQUENCY              ; 0                           ; Untyped                         ;
; DOWN_SPREAD                   ; 0                           ; Untyped                         ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                         ; Untyped                         ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                         ; Untyped                         ;
; CLK9_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK8_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK7_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK6_MULTIPLY_BY              ; 0                           ; Untyped                         ;
; CLK5_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK4_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK3_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK2_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK1_MULTIPLY_BY              ; 1                           ; Untyped                         ;
; CLK0_MULTIPLY_BY              ; 3                           ; Signed Integer                  ;
; CLK9_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK8_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK7_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK6_DIVIDE_BY                ; 0                           ; Untyped                         ;
; CLK5_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK4_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK3_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK2_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK1_DIVIDE_BY                ; 1                           ; Untyped                         ;
; CLK0_DIVIDE_BY                ; 15625                       ; Signed Integer                  ;
; CLK9_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK8_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK7_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK6_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK5_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK4_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK3_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK2_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK1_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK0_PHASE_SHIFT              ; 0                           ; Untyped                         ;
; CLK5_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK4_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK3_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK2_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK1_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK0_TIME_DELAY               ; 0                           ; Untyped                         ;
; CLK9_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK8_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK7_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK6_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK5_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK4_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK3_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK2_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK1_DUTY_CYCLE               ; 50                          ; Untyped                         ;
; CLK0_DUTY_CYCLE               ; 50                          ; Signed Integer                  ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                         ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                         ;
; LOCK_WINDOW_UI                ;  0.05                       ; Untyped                         ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                      ; Untyped                         ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                      ; Untyped                         ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                      ; Untyped                         ;
; DPA_MULTIPLY_BY               ; 0                           ; Untyped                         ;
; DPA_DIVIDE_BY                 ; 1                           ; Untyped                         ;
; DPA_DIVIDER                   ; 0                           ; Untyped                         ;
; EXTCLK3_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK2_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK1_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK0_MULTIPLY_BY           ; 1                           ; Untyped                         ;
; EXTCLK3_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK2_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK1_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK0_DIVIDE_BY             ; 1                           ; Untyped                         ;
; EXTCLK3_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK2_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK1_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK0_PHASE_SHIFT           ; 0                           ; Untyped                         ;
; EXTCLK3_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK2_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK1_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK0_TIME_DELAY            ; 0                           ; Untyped                         ;
; EXTCLK3_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; EXTCLK2_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; EXTCLK1_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; EXTCLK0_DUTY_CYCLE            ; 50                          ; Untyped                         ;
; VCO_MULTIPLY_BY               ; 0                           ; Untyped                         ;
; VCO_DIVIDE_BY                 ; 0                           ; Untyped                         ;
; SCLKOUT0_PHASE_SHIFT          ; 0                           ; Untyped                         ;
; SCLKOUT1_PHASE_SHIFT          ; 0                           ; Untyped                         ;
; VCO_MIN                       ; 0                           ; Untyped                         ;
; VCO_MAX                       ; 0                           ; Untyped                         ;
; VCO_CENTER                    ; 0                           ; Untyped                         ;
; PFD_MIN                       ; 0                           ; Untyped                         ;
; PFD_MAX                       ; 0                           ; Untyped                         ;
; M_INITIAL                     ; 0                           ; Untyped                         ;
; M                             ; 0                           ; Untyped                         ;
; N                             ; 1                           ; Untyped                         ;
; M2                            ; 1                           ; Untyped                         ;
; N2                            ; 1                           ; Untyped                         ;
; SS                            ; 1                           ; Untyped                         ;
; C0_HIGH                       ; 0                           ; Untyped                         ;
; C1_HIGH                       ; 0                           ; Untyped                         ;
; C2_HIGH                       ; 0                           ; Untyped                         ;
; C3_HIGH                       ; 0                           ; Untyped                         ;
; C4_HIGH                       ; 0                           ; Untyped                         ;
; C5_HIGH                       ; 0                           ; Untyped                         ;
; C6_HIGH                       ; 0                           ; Untyped                         ;
; C7_HIGH                       ; 0                           ; Untyped                         ;
; C8_HIGH                       ; 0                           ; Untyped                         ;
; C9_HIGH                       ; 0                           ; Untyped                         ;
; C0_LOW                        ; 0                           ; Untyped                         ;
; C1_LOW                        ; 0                           ; Untyped                         ;
; C2_LOW                        ; 0                           ; Untyped                         ;
; C3_LOW                        ; 0                           ; Untyped                         ;
; C4_LOW                        ; 0                           ; Untyped                         ;
; C5_LOW                        ; 0                           ; Untyped                         ;
; C6_LOW                        ; 0                           ; Untyped                         ;
; C7_LOW                        ; 0                           ; Untyped                         ;
; C8_LOW                        ; 0                           ; Untyped                         ;
; C9_LOW                        ; 0                           ; Untyped                         ;
; C0_INITIAL                    ; 0                           ; Untyped                         ;
; C1_INITIAL                    ; 0                           ; Untyped                         ;
; C2_INITIAL                    ; 0                           ; Untyped                         ;
; C3_INITIAL                    ; 0                           ; Untyped                         ;
; C4_INITIAL                    ; 0                           ; Untyped                         ;
; C5_INITIAL                    ; 0                           ; Untyped                         ;
; C6_INITIAL                    ; 0                           ; Untyped                         ;
; C7_INITIAL                    ; 0                           ; Untyped                         ;
; C8_INITIAL                    ; 0                           ; Untyped                         ;
; C9_INITIAL                    ; 0                           ; Untyped                         ;
; C0_MODE                       ; BYPASS                      ; Untyped                         ;
; C1_MODE                       ; BYPASS                      ; Untyped                         ;
; C2_MODE                       ; BYPASS                      ; Untyped                         ;
; C3_MODE                       ; BYPASS                      ; Untyped                         ;
; C4_MODE                       ; BYPASS                      ; Untyped                         ;
; C5_MODE                       ; BYPASS                      ; Untyped                         ;
; C6_MODE                       ; BYPASS                      ; Untyped                         ;
; C7_MODE                       ; BYPASS                      ; Untyped                         ;
; C8_MODE                       ; BYPASS                      ; Untyped                         ;
; C9_MODE                       ; BYPASS                      ; Untyped                         ;
; C0_PH                         ; 0                           ; Untyped                         ;
; C1_PH                         ; 0                           ; Untyped                         ;
; C2_PH                         ; 0                           ; Untyped                         ;
; C3_PH                         ; 0                           ; Untyped                         ;
; C4_PH                         ; 0                           ; Untyped                         ;
; C5_PH                         ; 0                           ; Untyped                         ;
; C6_PH                         ; 0                           ; Untyped                         ;
; C7_PH                         ; 0                           ; Untyped                         ;
; C8_PH                         ; 0                           ; Untyped                         ;
; C9_PH                         ; 0                           ; Untyped                         ;
; L0_HIGH                       ; 1                           ; Untyped                         ;
; L1_HIGH                       ; 1                           ; Untyped                         ;
; G0_HIGH                       ; 1                           ; Untyped                         ;
; G1_HIGH                       ; 1                           ; Untyped                         ;
; G2_HIGH                       ; 1                           ; Untyped                         ;
; G3_HIGH                       ; 1                           ; Untyped                         ;
; E0_HIGH                       ; 1                           ; Untyped                         ;
; E1_HIGH                       ; 1                           ; Untyped                         ;
; E2_HIGH                       ; 1                           ; Untyped                         ;
; E3_HIGH                       ; 1                           ; Untyped                         ;
; L0_LOW                        ; 1                           ; Untyped                         ;
; L1_LOW                        ; 1                           ; Untyped                         ;
; G0_LOW                        ; 1                           ; Untyped                         ;
; G1_LOW                        ; 1                           ; Untyped                         ;
; G2_LOW                        ; 1                           ; Untyped                         ;
; G3_LOW                        ; 1                           ; Untyped                         ;
; E0_LOW                        ; 1                           ; Untyped                         ;
; E1_LOW                        ; 1                           ; Untyped                         ;
; E2_LOW                        ; 1                           ; Untyped                         ;
; E3_LOW                        ; 1                           ; Untyped                         ;
; L0_INITIAL                    ; 1                           ; Untyped                         ;
; L1_INITIAL                    ; 1                           ; Untyped                         ;
; G0_INITIAL                    ; 1                           ; Untyped                         ;
; G1_INITIAL                    ; 1                           ; Untyped                         ;
; G2_INITIAL                    ; 1                           ; Untyped                         ;
; G3_INITIAL                    ; 1                           ; Untyped                         ;
; E0_INITIAL                    ; 1                           ; Untyped                         ;
; E1_INITIAL                    ; 1                           ; Untyped                         ;
; E2_INITIAL                    ; 1                           ; Untyped                         ;
; E3_INITIAL                    ; 1                           ; Untyped                         ;
; L0_MODE                       ; BYPASS                      ; Untyped                         ;
; L1_MODE                       ; BYPASS                      ; Untyped                         ;
; G0_MODE                       ; BYPASS                      ; Untyped                         ;
; G1_MODE                       ; BYPASS                      ; Untyped                         ;
; G2_MODE                       ; BYPASS                      ; Untyped                         ;
; G3_MODE                       ; BYPASS                      ; Untyped                         ;
; E0_MODE                       ; BYPASS                      ; Untyped                         ;
; E1_MODE                       ; BYPASS                      ; Untyped                         ;
; E2_MODE                       ; BYPASS                      ; Untyped                         ;
; E3_MODE                       ; BYPASS                      ; Untyped                         ;
; L0_PH                         ; 0                           ; Untyped                         ;
; L1_PH                         ; 0                           ; Untyped                         ;
; G0_PH                         ; 0                           ; Untyped                         ;
; G1_PH                         ; 0                           ; Untyped                         ;
; G2_PH                         ; 0                           ; Untyped                         ;
; G3_PH                         ; 0                           ; Untyped                         ;
; E0_PH                         ; 0                           ; Untyped                         ;
; E1_PH                         ; 0                           ; Untyped                         ;
; E2_PH                         ; 0                           ; Untyped                         ;
; E3_PH                         ; 0                           ; Untyped                         ;
; M_PH                          ; 0                           ; Untyped                         ;
; C1_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C2_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C3_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C4_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C5_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C6_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C7_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C8_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; C9_USE_CASC_IN                ; OFF                         ; Untyped                         ;
; CLK0_COUNTER                  ; G0                          ; Untyped                         ;
; CLK1_COUNTER                  ; G0                          ; Untyped                         ;
; CLK2_COUNTER                  ; G0                          ; Untyped                         ;
; CLK3_COUNTER                  ; G0                          ; Untyped                         ;
; CLK4_COUNTER                  ; G0                          ; Untyped                         ;
; CLK5_COUNTER                  ; G0                          ; Untyped                         ;
; CLK6_COUNTER                  ; E0                          ; Untyped                         ;
; CLK7_COUNTER                  ; E1                          ; Untyped                         ;
; CLK8_COUNTER                  ; E2                          ; Untyped                         ;
; CLK9_COUNTER                  ; E3                          ; Untyped                         ;
; L0_TIME_DELAY                 ; 0                           ; Untyped                         ;
; L1_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G0_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G1_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G2_TIME_DELAY                 ; 0                           ; Untyped                         ;
; G3_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E0_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E1_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E2_TIME_DELAY                 ; 0                           ; Untyped                         ;
; E3_TIME_DELAY                 ; 0                           ; Untyped                         ;
; M_TIME_DELAY                  ; 0                           ; Untyped                         ;
; N_TIME_DELAY                  ; 0                           ; Untyped                         ;
; EXTCLK3_COUNTER               ; E3                          ; Untyped                         ;
; EXTCLK2_COUNTER               ; E2                          ; Untyped                         ;
; EXTCLK1_COUNTER               ; E1                          ; Untyped                         ;
; EXTCLK0_COUNTER               ; E0                          ; Untyped                         ;
; ENABLE0_COUNTER               ; L0                          ; Untyped                         ;
; ENABLE1_COUNTER               ; L0                          ; Untyped                         ;
; CHARGE_PUMP_CURRENT           ; 2                           ; Untyped                         ;
; LOOP_FILTER_R                 ;  1.000000                   ; Untyped                         ;
; LOOP_FILTER_C                 ; 5                           ; Untyped                         ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                        ; Untyped                         ;
; LOOP_FILTER_R_BITS            ; 9999                        ; Untyped                         ;
; LOOP_FILTER_C_BITS            ; 9999                        ; Untyped                         ;
; VCO_POST_SCALE                ; 0                           ; Untyped                         ;
; CLK2_OUTPUT_FREQUENCY         ; 0                           ; Untyped                         ;
; CLK1_OUTPUT_FREQUENCY         ; 0                           ; Untyped                         ;
; CLK0_OUTPUT_FREQUENCY         ; 0                           ; Untyped                         ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E                ; Untyped                         ;
; PORT_CLKENA0                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA1                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA2                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA3                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA4                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKENA5                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_EXTCLK0                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLK1                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLK2                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_EXTCLK3                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKBAD0                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKBAD1                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK0                     ; PORT_USED                   ; Untyped                         ;
; PORT_CLK1                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK2                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK3                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK4                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK5                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK6                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK7                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK8                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLK9                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANDATA                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANDATAOUT              ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANDONE                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKLOSS                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_INCLK1                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_INCLK0                   ; PORT_USED                   ; Untyped                         ;
; PORT_FBIN                     ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PLLENA                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CLKSWITCH                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_ARESET                   ; PORT_USED                   ; Untyped                         ;
; PORT_PFDENA                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANCLK                  ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANACLR                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANREAD                 ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANWRITE                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_LOCKED                   ; PORT_UNUSED                 ; Untyped                         ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED                 ; Untyped                         ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_PHASEDONE                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PHASESTEP                ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED                 ; Untyped                         ;
; PORT_SCANCLKENA               ; PORT_UNUSED                 ; Untyped                         ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED                 ; Untyped                         ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY           ; Untyped                         ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY           ; Untyped                         ;
; M_TEST_SOURCE                 ; 5                           ; Untyped                         ;
; C0_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C1_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C2_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C3_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C4_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C5_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C6_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C7_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C8_TEST_SOURCE                ; 5                           ; Untyped                         ;
; C9_TEST_SOURCE                ; 5                           ; Untyped                         ;
; CBXI_PARAMETER                ; lab6_pll2_altpll            ; Untyped                         ;
; VCO_FREQUENCY_CONTROL         ; AUTO                        ; Untyped                         ;
; VCO_PHASE_SHIFT_STEP          ; 0                           ; Untyped                         ;
; WIDTH_CLOCK                   ; 5                           ; Signed Integer                  ;
; WIDTH_PHASECOUNTERSELECT      ; 4                           ; Untyped                         ;
; USING_FBMIMICBIDIR_PORT       ; OFF                         ; Untyped                         ;
; DEVICE_FAMILY                 ; Cyclone IV E                ; Untyped                         ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                      ; Untyped                         ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                         ; Untyped                         ;
; AUTO_CARRY_CHAINS             ; ON                          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS          ; OFF                         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS           ; ON                          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS        ; OFF                         ; IGNORE_CASCADE                  ;
+-------------------------------+-----------------------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0                     ;
+------------------------------------------------+--------------+---------------------+
; Parameter Name                                 ; Value        ; Type                ;
+------------------------------------------------+--------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 12           ; Untyped             ;
; LPM_WIDTHB                                     ; 10           ; Untyped             ;
; LPM_WIDTHP                                     ; 22           ; Untyped             ;
; LPM_WIDTHR                                     ; 22           ; Untyped             ;
; LPM_WIDTHS                                     ; 1            ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0            ; Untyped             ;
; LATENCY                                        ; 0            ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; YES          ; Untyped             ;
; USE_EAB                                        ; OFF          ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5            ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL       ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING      ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped             ;
+------------------------------------------------+--------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Div0 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 22             ; Untyped                ;
; LPM_WIDTHD             ; 11             ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_dkm ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                     ;
+-------------------------------+--------------------------------------------------+
; Name                          ; Value                                            ;
+-------------------------------+--------------------------------------------------+
; Number of entity instances    ; 2                                                ;
; Entity Instance               ; lab6_pll1:lab6_pll1_inst|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                           ;
;     -- PLL_TYPE               ; AUTO                                             ;
;     -- PRIMARY_CLOCK          ; INCLK0                                           ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                            ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                ;
;     -- VCO_MULTIPLY_BY        ; 0                                                ;
;     -- VCO_DIVIDE_BY          ; 0                                                ;
; Entity Instance               ; lab6_pll2:lab6_pll2_inst|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                           ;
;     -- PLL_TYPE               ; AUTO                                             ;
;     -- PRIMARY_CLOCK          ; INCLK0                                           ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                            ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                ;
;     -- VCO_MULTIPLY_BY        ; 0                                                ;
;     -- VCO_DIVIDE_BY          ; 0                                                ;
+-------------------------------+--------------------------------------------------+


+--------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance         ;
+---------------------------------------+----------------+
; Name                                  ; Value          ;
+---------------------------------------+----------------+
; Number of entity instances            ; 1              ;
; Entity Instance                       ; lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 12             ;
;     -- LPM_WIDTHB                     ; 10             ;
;     -- LPM_WIDTHP                     ; 22             ;
;     -- LPM_REPRESENTATION             ; UNSIGNED       ;
;     -- INPUT_A_IS_CONSTANT            ; NO             ;
;     -- INPUT_B_IS_CONSTANT            ; YES            ;
;     -- USE_EAB                        ; OFF            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx             ;
+---------------------------------------+----------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "uart_rcv:uart_rcv_0"                                                                                ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; uart_rx_output[7..3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 22                          ;
; cycloneiii_ff         ; 95                          ;
;     CLR               ; 42                          ;
;     ENA CLR           ; 53                          ;
; cycloneiii_lcell_comb ; 620                         ;
;     arith             ; 167                         ;
;         2 data inputs ; 34                          ;
;         3 data inputs ; 133                         ;
;     normal            ; 453                         ;
;         0 data inputs ; 14                          ;
;         1 data inputs ; 15                          ;
;         2 data inputs ; 164                         ;
;         3 data inputs ; 29                          ;
;         4 data inputs ; 231                         ;
; cycloneiii_pll        ; 2                           ;
;                       ;                             ;
; Max LUT depth         ; 43.40                       ;
; Average LUT depth     ; 33.79                       ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:03     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition
    Info: Processing started: Wed May 25 16:53:08 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab6 -c lab6
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file lab6.sv
    Info (12023): Found entity 1: lab6 File: /home/traylor/fpga/lab6/lab6.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file debouncer.sv
    Info (12023): Found entity 1: debouncer File: /home/traylor/fpga/lab6/debouncer.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file bcd2_7seg.sv
    Info (12023): Found entity 1: bcd2_7seg File: /home/traylor/fpga/lab6/bcd2_7seg.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file bin2bcd.sv
    Info (12023): Found entity 1: bin2bcd File: /home/traylor/fpga/lab6/bin2bcd.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file adc_control.sv
    Info (12023): Found entity 1: adc_control File: /home/traylor/fpga/lab6/adc_control.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file lab6_pll1.v
    Info (12023): Found entity 1: lab6_pll1 File: /home/traylor/fpga/lab6/lab6_pll1.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file lab6_pll2.v
    Info (12023): Found entity 1: lab6_pll2 File: /home/traylor/fpga/lab6/lab6_pll2.v Line: 40
Info (12127): Elaborating entity "lab6" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at lab6.sv(54): object "adc_input_mux_addr0" assigned a value but never read File: /home/traylor/fpga/lab6/lab6.sv Line: 54
Warning (10036): Verilog HDL or VHDL warning at lab6.sv(55): object "adc_input_mux_addr1" assigned a value but never read File: /home/traylor/fpga/lab6/lab6.sv Line: 55
Warning (10036): Verilog HDL or VHDL warning at lab6.sv(56): object "adc_input_mux_addr2" assigned a value but never read File: /home/traylor/fpga/lab6/lab6.sv Line: 56
Warning (10958): SystemVerilog warning at lab6.sv(191): unique or priority keyword makes case statement complete File: /home/traylor/fpga/lab6/lab6.sv Line: 191
Info (10264): Verilog HDL Case Statement information at lab6.sv(433): all case item expressions in this case statement are onehot File: /home/traylor/fpga/lab6/lab6.sv Line: 433
Info (12128): Elaborating entity "adc_control" for hierarchy "adc_control:adc_control_0" File: /home/traylor/fpga/lab6/lab6.sv Line: 150
Warning (10958): SystemVerilog warning at adc_control.sv(57): unique or priority keyword makes case statement complete File: /home/traylor/fpga/lab6/adc_control.sv Line: 57
Warning (12125): Using design file uart_rcv.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info (12023): Found entity 1: uart_rcv File: /home/traylor/fpga/lab6/uart_rcv.sv Line: 1
Info (12128): Elaborating entity "uart_rcv" for hierarchy "uart_rcv:uart_rcv_0" File: /home/traylor/fpga/lab6/lab6.sv Line: 156
Info (12128): Elaborating entity "bin2bcd" for hierarchy "bin2bcd:bin2bcd_0" File: /home/traylor/fpga/lab6/lab6.sv Line: 167
Info (12128): Elaborating entity "bcd2_7seg" for hierarchy "bcd2_7seg:bcd2_7seg_0" File: /home/traylor/fpga/lab6/lab6.sv Line: 172
Warning (10958): SystemVerilog warning at bcd2_7seg.sv(11): unique or priority keyword makes case statement complete File: /home/traylor/fpga/lab6/bcd2_7seg.sv Line: 11
Info (12128): Elaborating entity "lab6_pll1" for hierarchy "lab6_pll1:lab6_pll1_inst" File: /home/traylor/fpga/lab6/lab6.sv Line: 278
Info (12128): Elaborating entity "altpll" for hierarchy "lab6_pll1:lab6_pll1_inst|altpll:altpll_component" File: /home/traylor/fpga/lab6/lab6_pll1.v Line: 108
Info (12130): Elaborated megafunction instantiation "lab6_pll1:lab6_pll1_inst|altpll:altpll_component" File: /home/traylor/fpga/lab6/lab6_pll1.v Line: 108
Info (12133): Instantiated megafunction "lab6_pll1:lab6_pll1_inst|altpll:altpll_component" with the following parameter: File: /home/traylor/fpga/lab6/lab6_pll1.v Line: 108
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "50"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "3"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "12500"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "clk2_divide_by" = "15625"
    Info (12134): Parameter "clk2_duty_cycle" = "50"
    Info (12134): Parameter "clk2_multiply_by" = "48"
    Info (12134): Parameter "clk2_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=lab6_pll1"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_USED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_USED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/lab6_pll1_altpll1.v
    Info (12023): Found entity 1: lab6_pll1_altpll1 File: /home/traylor/fpga/lab6/db/lab6_pll1_altpll1.v Line: 30
Info (12128): Elaborating entity "lab6_pll1_altpll1" for hierarchy "lab6_pll1:lab6_pll1_inst|altpll:altpll_component|lab6_pll1_altpll1:auto_generated" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (12128): Elaborating entity "lab6_pll2" for hierarchy "lab6_pll2:lab6_pll2_inst" File: /home/traylor/fpga/lab6/lab6.sv Line: 284
Info (12128): Elaborating entity "altpll" for hierarchy "lab6_pll2:lab6_pll2_inst|altpll:altpll_component" File: /home/traylor/fpga/lab6/lab6_pll2.v Line: 100
Info (12130): Elaborated megafunction instantiation "lab6_pll2:lab6_pll2_inst|altpll:altpll_component" File: /home/traylor/fpga/lab6/lab6_pll2.v Line: 100
Info (12133): Instantiated megafunction "lab6_pll2:lab6_pll2_inst|altpll:altpll_component" with the following parameter: File: /home/traylor/fpga/lab6/lab6_pll2.v Line: 100
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "15625"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "3"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=lab6_pll2"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_USED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/lab6_pll2_altpll.v
    Info (12023): Found entity 1: lab6_pll2_altpll File: /home/traylor/fpga/lab6/db/lab6_pll2_altpll.v Line: 30
Info (12128): Elaborating entity "lab6_pll2_altpll" for hierarchy "lab6_pll2:lab6_pll2_inst|altpll:altpll_component|lab6_pll2_altpll:auto_generated" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (278001): Inferred 2 megafunctions from design logic
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult0" File: /home/traylor/fpga/lab6/lab6.sv Line: 159
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div0" File: /home/traylor/fpga/lab6/lab6.sv Line: 159
Info (12130): Elaborated megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/fpga/lab6/lab6.sv Line: 159
Info (12133): Instantiated megafunction "lpm_mult:Mult0" with the following parameter: File: /home/traylor/fpga/lab6/lab6.sv Line: 159
    Info (12134): Parameter "LPM_WIDTHA" = "12"
    Info (12134): Parameter "LPM_WIDTHB" = "10"
    Info (12134): Parameter "LPM_WIDTHP" = "22"
    Info (12134): Parameter "LPM_WIDTHR" = "22"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 308
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/multcore.tdf Line: 229
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_ngh.tdf
    Info (12023): Found entity 1: add_sub_ngh File: /home/traylor/fpga/lab6/db/add_sub_ngh.tdf Line: 23
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_rgh.tdf
    Info (12023): Found entity 1: add_sub_rgh File: /home/traylor/fpga/lab6/db/add_sub_rgh.tdf Line: 23
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "lpm_mult:Mult0" File: /home/traylor/altera_lite/15.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 351
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div0" File: /home/traylor/fpga/lab6/lab6.sv Line: 159
Info (12133): Instantiated megafunction "lpm_divide:Div0" with the following parameter: File: /home/traylor/fpga/lab6/lab6.sv Line: 159
    Info (12134): Parameter "LPM_WIDTHN" = "22"
    Info (12134): Parameter "LPM_WIDTHD" = "11"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_dkm.tdf
    Info (12023): Found entity 1: lpm_divide_dkm File: /home/traylor/fpga/lab6/db/lpm_divide_dkm.tdf Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_5nh.tdf
    Info (12023): Found entity 1: sign_div_unsign_5nh File: /home/traylor/fpga/lab6/db/sign_div_unsign_5nh.tdf Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_u9f.tdf
    Info (12023): Found entity 1: alt_u_div_u9f File: /home/traylor/fpga/lab6/db/alt_u_div_u9f.tdf Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf
    Info (12023): Found entity 1: add_sub_7pc File: /home/traylor/fpga/lab6/db/add_sub_7pc.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf
    Info (12023): Found entity 1: add_sub_8pc File: /home/traylor/fpga/lab6/db/add_sub_8pc.tdf Line: 23
Info (13000): Registers with preset signals will power-up high File: /home/traylor/fpga/lab6/adc_control.sv Line: 49
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "segment_data[0]" is stuck at VCC File: /home/traylor/fpga/lab6/lab6.sv Line: 7
    Warning (13410): Pin "enable3to8_n" is stuck at GND File: /home/traylor/fpga/lab6/lab6.sv Line: 12
    Warning (13410): Pin "pwm_output" is stuck at GND File: /home/traylor/fpga/lab6/lab6.sv Line: 13
Info (286030): Timing-Driven Synthesis is running
Info (17049): 14 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 691 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 4 input pins
    Info (21059): Implemented 18 output pins
    Info (21061): Implemented 667 logic cells
    Info (21065): Implemented 2 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Peak virtual memory: 1220 megabytes
    Info: Processing ended: Wed May 25 16:53:24 2016
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:22


