TimeQuest Timing Analyzer report for lab6
Sat Jun 18 03:46:03 2016
Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Timing Closure Recommendations
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'adc_control:adc_control_0|s_clk'
 13. Slow 1200mV 85C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Setup: 'digit_clk'
 15. Slow 1200mV 85C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'
 16. Slow 1200mV 85C Model Setup: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'
 18. Slow 1200mV 85C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'
 19. Slow 1200mV 85C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'
 21. Slow 1200mV 85C Model Hold: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'digit_clk'
 23. Slow 1200mV 85C Model Hold: 'adc_control:adc_control_0|s_clk'
 24. Slow 1200mV 85C Model Recovery: 'adc_control:adc_control_0|adc_ps.STOP'
 25. Slow 1200mV 85C Model Removal: 'adc_control:adc_control_0|adc_ps.STOP'
 26. Slow 1200mV 85C Model Metastability Summary
 27. Slow 1200mV 0C Model Fmax Summary
 28. Slow 1200mV 0C Model Setup Summary
 29. Slow 1200mV 0C Model Hold Summary
 30. Slow 1200mV 0C Model Recovery Summary
 31. Slow 1200mV 0C Model Removal Summary
 32. Slow 1200mV 0C Model Minimum Pulse Width Summary
 33. Slow 1200mV 0C Model Setup: 'adc_control:adc_control_0|s_clk'
 34. Slow 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'
 35. Slow 1200mV 0C Model Setup: 'digit_clk'
 36. Slow 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'
 37. Slow 1200mV 0C Model Setup: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'
 38. Slow 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'
 39. Slow 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'
 40. Slow 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'
 42. Slow 1200mV 0C Model Hold: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'
 43. Slow 1200mV 0C Model Hold: 'digit_clk'
 44. Slow 1200mV 0C Model Hold: 'adc_control:adc_control_0|s_clk'
 45. Slow 1200mV 0C Model Recovery: 'adc_control:adc_control_0|adc_ps.STOP'
 46. Slow 1200mV 0C Model Removal: 'adc_control:adc_control_0|adc_ps.STOP'
 47. Slow 1200mV 0C Model Metastability Summary
 48. Fast 1200mV 0C Model Setup Summary
 49. Fast 1200mV 0C Model Hold Summary
 50. Fast 1200mV 0C Model Recovery Summary
 51. Fast 1200mV 0C Model Removal Summary
 52. Fast 1200mV 0C Model Minimum Pulse Width Summary
 53. Fast 1200mV 0C Model Setup: 'adc_control:adc_control_0|s_clk'
 54. Fast 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'
 55. Fast 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'
 56. Fast 1200mV 0C Model Setup: 'digit_clk'
 57. Fast 1200mV 0C Model Setup: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'
 58. Fast 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'
 59. Fast 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'
 60. Fast 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'
 61. Fast 1200mV 0C Model Hold: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'
 62. Fast 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'
 63. Fast 1200mV 0C Model Hold: 'digit_clk'
 64. Fast 1200mV 0C Model Hold: 'adc_control:adc_control_0|s_clk'
 65. Fast 1200mV 0C Model Recovery: 'adc_control:adc_control_0|adc_ps.STOP'
 66. Fast 1200mV 0C Model Removal: 'adc_control:adc_control_0|adc_ps.STOP'
 67. Fast 1200mV 0C Model Metastability Summary
 68. Multicorner Timing Analysis Summary
 69. Board Trace Model Assignments
 70. Input Transition Times
 71. Signal Integrity Metrics (Slow 1200mv 0c Model)
 72. Signal Integrity Metrics (Slow 1200mv 85c Model)
 73. Signal Integrity Metrics (Fast 1200mv 0c Model)
 74. Setup Transfers
 75. Hold Transfers
 76. Recovery Transfers
 77. Removal Transfers
 78. Report TCCS
 79. Report RSKM
 80. Unconstrained Paths Summary
 81. Clock Status Summary
 82. Unconstrained Input Ports
 83. Unconstrained Output Ports
 84. Unconstrained Input Ports
 85. Unconstrained Output Ports
 86. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+-----------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                           ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition ;
; Timing Analyzer       ; TimeQuest                                           ;
; Revision Name         ; lab6                                                ;
; Device Family         ; Cyclone IV E                                        ;
; Device Name           ; EP4CE22F17C6                                        ;
; Timing Models         ; Final                                               ;
; Delay Model           ; Combined                                            ;
; Rise/Fall Delays      ; Enabled                                             ;
+-----------------------+-----------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                         ;
+------------------------------------------------------------+-----------+------------+------------+-------+------------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+--------------------------------------------------------------+----------------------------------------------------------------+
; Clock Name                                                 ; Type      ; Period     ; Frequency  ; Rise  ; Fall       ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master     ; Source                                                       ; Targets                                                        ;
+------------------------------------------------------------+-----------+------------+------------+-------+------------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+--------------------------------------------------------------+----------------------------------------------------------------+
; adc_control:adc_control_0|adc_ps.STOP                      ; Base      ; 1.000      ; 1000.0 MHz ; 0.000 ; 0.500      ;            ;           ;             ;       ;        ;           ;            ;          ;            ;                                                              ; { adc_control:adc_control_0|adc_ps.STOP }                      ;
; adc_control:adc_control_0|s_clk                            ; Base      ; 1.000      ; 1000.0 MHz ; 0.000 ; 0.500      ;            ;           ;             ;       ;        ;           ;            ;          ;            ;                                                              ; { adc_control:adc_control_0|s_clk }                            ;
; digit_clk                                                  ; Base      ; 1.000      ; 1000.0 MHz ; 0.000 ; 0.500      ;            ;           ;             ;       ;        ;           ;            ;          ;            ;                                                              ; { digit_clk }                                                  ;
; inclk0_sig                                                 ; Base      ; 20.000     ; 50.0 MHz   ; 0.000 ; 10.000     ;            ;           ;             ;       ;        ;           ;            ;          ;            ;                                                              ; { inclk0_sig }                                                 ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 333.333    ; 3.0 MHz    ; 0.000 ; 166.666    ; 50.00      ; 50        ; 3           ;       ;        ;           ;            ; false    ; inclk0_sig ; lab6_pll1_inst|altpll_component|auto_generated|pll1|inclk[0] ; { lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] } ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 250000.000 ; 0.0 MHz    ; 0.000 ; 125000.000 ; 50.00      ; 12500     ; 1           ;       ;        ;           ;            ; false    ; inclk0_sig ; lab6_pll1_inst|altpll_component|auto_generated|pll1|inclk[0] ; { lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] } ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 6510.416   ; 0.15 MHz   ; 0.000 ; 3255.208   ; 50.00      ; 15625     ; 48          ;       ;        ;           ;            ; false    ; inclk0_sig ; lab6_pll1_inst|altpll_component|auto_generated|pll1|inclk[0] ; { lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] } ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 104166.666 ; 0.01 MHz   ; 0.000 ; 52083.333  ; 50.00      ; 15625     ; 3           ;       ;        ;           ;            ; false    ; inclk0_sig ; lab6_pll2_inst|altpll_component|auto_generated|pll1|inclk[0] ; { lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] } ;
+------------------------------------------------------------+-----------+------------+------------+-------+------------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+--------------------------------------------------------------+----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                         ;
+------------+-----------------+------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                 ; Note                                           ;
+------------+-----------------+------------------------------------------------------------+------------------------------------------------+
; 396.51 MHz ; 396.51 MHz      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 430.66 MHz ; 430.66 MHz      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ;                                                ;
; 470.81 MHz ; 470.81 MHz      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 554.02 MHz ; 500.0 MHz       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; limit due to minimum period restriction (tmin) ;
; 649.77 MHz ; 500.0 MHz       ; digit_clk                                                  ; limit due to minimum period restriction (tmin) ;
; 909.09 MHz ; 500.0 MHz       ; adc_control:adc_control_0|s_clk                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+---------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                   ;
+------------------------------------------------------------+----------+---------------+
; Clock                                                      ; Slack    ; End Point TNS ;
+------------------------------------------------------------+----------+---------------+
; adc_control:adc_control_0|s_clk                            ; -2.232   ; -26.784       ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -1.406   ; -10.138       ;
; digit_clk                                                  ; -0.539   ; -1.129        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.530   ; -4.317        ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.264   ; -0.264        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6508.094 ; 0.000         ;
+------------------------------------------------------------+----------+---------------+


+-------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                  ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.207 ; -0.207        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.195 ; -0.195        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.358  ; 0.000         ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.358  ; 0.000         ;
; digit_clk                                                  ; 0.404  ; 0.000         ;
; adc_control:adc_control_0|s_clk                            ; 0.414  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                         ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; adc_control:adc_control_0|adc_ps.STOP ; -0.832 ; -0.832        ;
+---------------------------------------+--------+---------------+


+---------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                         ;
+---------------------------------------+-------+---------------+
; Clock                                 ; Slack ; End Point TNS ;
+---------------------------------------+-------+---------------+
; adc_control:adc_control_0|adc_ps.STOP ; 0.925 ; 0.000         ;
+---------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                       ;
+------------------------------------------------------------+------------+---------------+
; Clock                                                      ; Slack      ; End Point TNS ;
+------------------------------------------------------------+------------+---------------+
; adc_control:adc_control_0|s_clk                            ; -1.000     ; -12.000       ;
; digit_clk                                                  ; -1.000     ; -3.000        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; -1.000     ; -1.000        ;
; inclk0_sig                                                 ; 9.835      ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 166.415    ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 3254.955   ; 0.000         ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 52083.085  ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 124999.747 ; 0.000         ;
+------------------------------------------------------------+------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'adc_control:adc_control_0|s_clk'                                                                                                                                                ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node             ; Launch Clock                                               ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.232 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.638      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -2.117 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.490      ; 4.523      ;
; -0.100 ; adc_sr_data_out[2]                     ; adc_sr_data_out[3]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 1.032      ;
; -0.075 ; adc_sr_data_out[4]                     ; adc_sr_data_out[5]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 1.007      ;
; -0.059 ; adc_sr_data_out[3]                     ; adc_sr_data_out[4]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.991      ;
; -0.056 ; adc_sr_data_out[8]                     ; adc_sr_data_out[9]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.988      ;
; 0.047  ; adc_sr_data_out[5]                     ; adc_sr_data_out[6]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.885      ;
; 0.056  ; adc_sr_data_out[0]                     ; adc_sr_data_out[1]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.876      ;
; 0.076  ; adc_sr_data_out[1]                     ; adc_sr_data_out[2]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.856      ;
; 0.077  ; adc_sr_data_out[7]                     ; adc_sr_data_out[8]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.855      ;
; 0.079  ; adc_sr_data_out[9]                     ; adc_sr_data_out[10] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.853      ;
; 0.080  ; adc_sr_data_out[6]                     ; adc_sr_data_out[7]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.852      ;
; 0.192  ; adc_sr_data_out[10]                    ; adc_sr_data_out[11] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.063     ; 0.740      ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                    ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                              ; To Node                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -1.406  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.455      ;
; -1.406  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.455      ;
; -1.406  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.455      ;
; -1.406  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.455      ;
; -1.349  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.398      ;
; -1.348  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.397      ;
; -1.348  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.397      ;
; -1.348  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.397      ;
; -1.348  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.397      ;
; -1.284  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.333      ;
; -1.271  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.330      ;
; -1.244  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.293      ;
; -1.235  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.294      ;
; -1.180  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 1.229      ;
; -0.610  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 0.659      ;
; -0.588  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.086     ; 0.637      ;
; 329.217 ; count_2hz[7]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.945      ;
; 329.364 ; count_2hz[5]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.798      ;
; 329.459 ; count_2hz[6]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.703      ;
; 329.598 ; count_2hz[4]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.564      ;
; 329.708 ; count_2hz[0]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.454      ;
; 329.720 ; count_2hz[3]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.442      ;
; 329.814 ; count_2hz[2]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.348      ;
; 329.951 ; count_2hz[1]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.166     ; 3.211      ;
; 330.811 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 2.455      ;
; 331.011 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 2.255      ;
; 331.017 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 2.249      ;
; 331.497 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.769      ;
; 331.560 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.706      ;
; 331.560 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.706      ;
; 331.560 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.706      ;
; 331.560 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.706      ;
; 331.803 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.463      ;
; 331.809 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.457      ;
; 331.955 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.311      ;
; 331.964 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.302      ;
; 332.073 ; q0_2hz_sync                            ; two_hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.193      ;
; 332.087 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.179      ;
; 332.151 ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.115      ;
; 332.154 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.112      ;
; 332.265 ; two_hz_sync                            ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 1.001      ;
; 332.275 ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.991      ;
; 332.297 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.969      ;
; 332.301 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.965      ;
; 332.303 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.963      ;
; 332.399 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.867      ;
; 332.400 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.866      ;
; 332.407 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.859      ;
; 332.427 ; two_hz_sync                            ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.839      ;
; 332.531 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.735      ;
; 332.554 ; button_pulse_ps.PULSE                  ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.712      ;
; 332.558 ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.708      ;
; 332.575 ; button_pulse_ps.DETECT                 ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.691      ;
; 332.607 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.659      ;
; 332.607 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.659      ;
; 332.607 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.659      ;
; 332.629 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.637      ;
; 332.629 ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.062     ; 0.637      ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'digit_clk'                                                                         ;
+--------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node       ; To Node         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; -0.539 ; digit_seq_ps[2] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.473      ;
; -0.501 ; digit_seq_ps[2] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.435      ;
; -0.405 ; digit_seq_ps[0] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.339      ;
; -0.399 ; digit_seq_ps[0] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.333      ;
; -0.269 ; digit_seq_ps[1] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.203      ;
; -0.262 ; digit_seq_ps[1] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.196      ;
; -0.089 ; digit_seq_ps[2] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 1.023      ;
; 0.206  ; digit_seq_ps[1] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 1.000        ; -0.061     ; 0.728      ;
+--------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                         ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack      ; From Node       ; To Node         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.530     ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.530     ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 1.090      ;
; -0.077     ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.074     ; 0.637      ;
; 0.006      ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.006      ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 1.054      ;
; 0.401      ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.074     ; 0.659      ;
; 249998.195 ; count_2hz[1]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.738      ;
; 249998.199 ; count_2hz[0]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.734      ;
; 249998.201 ; count_2hz[1]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.732      ;
; 249998.269 ; count_2hz[0]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.664      ;
; 249998.306 ; count_2hz[3]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.627      ;
; 249998.311 ; count_2hz[1]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.622      ;
; 249998.311 ; count_2hz[2]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.622      ;
; 249998.312 ; count_2hz[3]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.621      ;
; 249998.315 ; count_2hz[0]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.618      ;
; 249998.317 ; count_2hz[1]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.616      ;
; 249998.385 ; count_2hz[0]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.548      ;
; 249998.388 ; count_2hz[2]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.545      ;
; 249998.421 ; count_2hz[5]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.512      ;
; 249998.422 ; count_2hz[3]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.511      ;
; 249998.427 ; count_2hz[1]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.506      ;
; 249998.427 ; count_2hz[5]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.506      ;
; 249998.427 ; count_2hz[2]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.506      ;
; 249998.428 ; count_2hz[4]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.505      ;
; 249998.428 ; count_2hz[3]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.505      ;
; 249998.431 ; count_2hz[0]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.502      ;
; 249998.433 ; count_2hz[1]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.500      ;
; 249998.501 ; count_2hz[0]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.432      ;
; 249998.504 ; count_2hz[2]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.429      ;
; 249998.506 ; count_2hz[4]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.427      ;
; 249998.543 ; count_2hz[2]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.390      ;
; 249998.544 ; count_2hz[4]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.389      ;
; 249998.547 ; count_2hz[0]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.386      ;
; 249998.547 ; count_2hz[6]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.386      ;
; 249998.931 ; count_2hz[0]    ; count_2hz[0]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 1.002      ;
; 249998.934 ; count_2hz[6]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.999      ;
; 249998.936 ; count_2hz[2]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.997      ;
; 249998.938 ; count_2hz[4]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.995      ;
; 249998.957 ; count_2hz[5]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.976      ;
; 249998.958 ; count_2hz[3]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.975      ;
; 249998.962 ; count_2hz[1]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.971      ;
; 249998.988 ; debounce_cnt[0] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.945      ;
; 249999.224 ; count_2hz[7]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.709      ;
; 249999.228 ; debounce_cnt[0] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.705      ;
; 249999.245 ; debounce_cnt[1] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.688      ;
; 249999.274 ; debounce_cnt[0] ; debounce_cnt[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.659      ;
; 249999.274 ; debounce_cnt[1] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.062     ; 0.659      ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                           ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack      ; From Node                ; To Node                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.264     ; q_stretch                ; q0_sync                  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 1.000        ; -0.529     ; 0.690      ;
; 104164.542 ; start_send_ps            ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.057      ;
; 104164.542 ; start_send_ps            ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.057      ;
; 104164.542 ; start_send_ps            ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.057      ;
; 104164.542 ; start_send_ps            ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.057      ;
; 104164.546 ; start_send_ps            ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.053      ;
; 104164.546 ; start_send_ps            ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.053      ;
; 104164.546 ; start_send_ps            ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 2.053      ;
; 104164.760 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.839      ;
; 104164.760 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.839      ;
; 104164.760 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.839      ;
; 104164.760 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.839      ;
; 104164.773 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.826      ;
; 104164.773 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.826      ;
; 104164.773 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.826      ;
; 104165.158 ; adc_data_rdy_stretch     ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.058     ; 1.445      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.352 ; start_send_ps            ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.247      ;
; 104165.463 ; serial_bit_cntr_ps.BIT_8 ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.136      ;
; 104165.502 ; adc_data_rdy_stretch     ; q0_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.061     ; 1.098      ;
; 104165.576 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 1.023      ;
; 104165.602 ; uart_main_ps.CHAR_5      ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.997      ;
; 104165.611 ; uart_main_ps.CHAR_1      ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.988      ;
; 104165.634 ; uart_main_ps.CHAR_0      ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.965      ;
; 104165.641 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.958      ;
; 104165.725 ; uart_main_ps.CHAR_3      ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.874      ;
; 104165.725 ; uart_main_ps.CHAR_2      ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.874      ;
; 104165.732 ; uart_main_ps.CHAR_6      ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.867      ;
; 104165.736 ; uart_main_ps.CHAR_4      ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.863      ;
; 104165.745 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.854      ;
; 104165.749 ; adc_data_rdy_stretch     ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.061     ; 0.851      ;
; 104165.753 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.846      ;
; 104165.766 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.833      ;
; 104165.766 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.833      ;
; 104165.767 ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.832      ;
; 104165.776 ; q0_sync                  ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.061     ; 0.824      ;
; 104165.846 ; uart_main_ps.CHAR_6      ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.753      ;
; 104165.889 ; serial_bit_cntr_ps.BIT_9 ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.710      ;
; 104165.910 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.689      ;
; 104165.911 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.688      ;
; 104165.914 ; q1_sync                  ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.061     ; 0.686      ;
; 104165.940 ; start_send_ps            ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.062     ; 0.659      ;
; 104165.941 ; adc_data_rdy_stretch     ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.061     ; 0.659      ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                       ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack    ; From Node                                               ; To Node                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 6508.094 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.239      ;
; 6508.094 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.239      ;
; 6508.094 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.239      ;
; 6508.167 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.166      ;
; 6508.167 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.166      ;
; 6508.167 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.166      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.182 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 2.151      ;
; 6508.339 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.994      ;
; 6508.339 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.994      ;
; 6508.339 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.994      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.394 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.939      ;
; 6508.469 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.864      ;
; 6508.469 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.864      ;
; 6508.469 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.864      ;
; 6508.532 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 1.816      ;
; 6508.605 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.744      ;
; 6508.605 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.744      ;
; 6508.637 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.712      ;
; 6508.691 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 1.657      ;
; 6508.699 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.650      ;
; 6508.710 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.639      ;
; 6508.726 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.623      ;
; 6508.743 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.606      ;
; 6508.770 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.579      ;
; 6508.792 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.557      ;
; 6508.798 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.551      ;
; 6508.817 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.532      ;
; 6508.817 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.532      ;
; 6508.862 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.487      ;
; 6508.882 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.467      ;
; 6508.910 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.439      ;
; 6508.930 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.419      ;
; 6508.934 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.415      ;
; 6508.951 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 1.397      ;
; 6508.992 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.357      ;
; 6509.010 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.339      ;
; 6509.012 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.337      ;
; 6509.020 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 1.328      ;
; 6509.054 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.295      ;
; 6509.081 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.268      ;
; 6509.089 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.260      ;
; 6509.106 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.243      ;
; 6509.175 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.174      ;
; 6509.184 ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.078     ; 1.149      ;
; 6509.264 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.085      ;
; 6509.265 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.084      ;
; 6509.305 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.044      ;
; 6509.306 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.043      ;
; 6509.323 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.026      ;
; 6509.336 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.013      ;
; 6509.348 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 1.001      ;
; 6509.361 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.987      ;
; 6509.504 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.845      ;
; 6509.504 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.845      ;
; 6509.505 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.844      ;
; 6509.506 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.843      ;
; 6509.507 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.842      ;
; 6509.509 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.840      ;
; 6509.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.834      ;
; 6509.515 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.833      ;
; 6509.516 ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.833      ;
; 6509.517 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.831      ;
; 6509.518 ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.831      ;
; 6509.562 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.787      ;
; 6509.635 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.714      ;
; 6509.636 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.713      ;
; 6509.637 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.712      ;
; 6509.648 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.701      ;
; 6509.658 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.690      ;
; 6509.659 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.689      ;
; 6509.659 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.689      ;
; 6509.660 ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.689      ;
; 6509.661 ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.688      ;
; 6509.661 ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.688      ;
; 6509.661 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.687      ;
; 6509.661 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.687      ;
; 6509.661 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.687      ;
; 6509.661 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.687      ;
; 6509.662 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.063     ; 0.686      ;
; 6509.690 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.659      ;
; 6509.690 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.659      ;
; 6509.690 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.659      ;
; 6509.712 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.637      ;
; 6509.712 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.637      ;
; 6509.712 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.637      ;
; 6509.712 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.637      ;
; 6509.712 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.062     ; 0.637      ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                      ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node       ; To Node         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.207 ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 0.577      ;
; 0.294  ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 0.578      ;
; 0.345  ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.345  ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.328      ; 1.129      ;
; 0.358  ; debounce_cnt[1] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.577      ;
; 0.361  ; debounce_cnt[0] ; debounce_cnt[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.580      ;
; 0.370  ; debounce_cnt[1] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.589      ;
; 0.381  ; debounce_cnt[0] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.600      ;
; 0.390  ; count_2hz[7]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.609      ;
; 0.557  ; count_2hz[1]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.776      ;
; 0.559  ; count_2hz[6]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.778      ;
; 0.561  ; count_2hz[5]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.780      ;
; 0.561  ; count_2hz[3]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.780      ;
; 0.562  ; count_2hz[4]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.781      ;
; 0.562  ; debounce_cnt[0] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.781      ;
; 0.563  ; count_2hz[2]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.782      ;
; 0.577  ; count_2hz[0]    ; count_2hz[0]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 0.796      ;
; 0.832  ; count_2hz[1]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.051      ;
; 0.835  ; count_2hz[5]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.054      ;
; 0.835  ; count_2hz[3]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.054      ;
; 0.847  ; count_2hz[6]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.066      ;
; 0.847  ; count_2hz[0]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.066      ;
; 0.849  ; count_2hz[4]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.068      ;
; 0.849  ; count_2hz[0]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.068      ;
; 0.850  ; count_2hz[2]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.069      ;
; 0.851  ; count_2hz[4]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.070      ;
; 0.852  ; count_2hz[2]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.071      ;
; 0.878  ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.878  ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.328      ; 1.162      ;
; 0.942  ; count_2hz[1]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.161      ;
; 0.944  ; count_2hz[1]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.163      ;
; 0.945  ; count_2hz[5]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.164      ;
; 0.945  ; count_2hz[3]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.164      ;
; 0.947  ; count_2hz[3]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.166      ;
; 0.959  ; count_2hz[0]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.178      ;
; 0.961  ; count_2hz[0]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.180      ;
; 0.961  ; count_2hz[4]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.180      ;
; 0.962  ; count_2hz[2]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.181      ;
; 0.964  ; count_2hz[2]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.183      ;
; 1.054  ; count_2hz[1]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.273      ;
; 1.056  ; count_2hz[1]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.275      ;
; 1.057  ; count_2hz[3]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.276      ;
; 1.071  ; count_2hz[0]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.290      ;
; 1.073  ; count_2hz[0]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.292      ;
; 1.074  ; count_2hz[2]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.293      ;
; 1.166  ; count_2hz[1]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.385      ;
; 1.183  ; count_2hz[0]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.062      ; 1.402      ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                    ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.195 ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 0.577      ;
; -0.194 ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 0.578      ;
; 0.358  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.372  ; button_pulse_ps.DETECT                 ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.591      ;
; 0.386  ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.605      ;
; 0.390  ; button_pulse_ps.PULSE                  ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.609      ;
; 0.404  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.176      ;
; 0.404  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.166      ;
; 0.407  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.626      ;
; 0.449  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.211      ;
; 0.457  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.229      ;
; 0.489  ; two_hz_sync                            ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.708      ;
; 0.494  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.266      ;
; 0.539  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.758      ;
; 0.547  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.766      ;
; 0.547  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.766      ;
; 0.566  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.338      ;
; 0.576  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.795      ;
; 0.580  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.799      ;
; 0.582  ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.801      ;
; 0.591  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.810      ;
; 0.597  ; two_hz_sync                            ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.816      ;
; 0.686  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.458      ;
; 0.686  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.458      ;
; 0.686  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.458      ;
; 0.686  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.458      ;
; 0.728  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.947      ;
; 0.734  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.953      ;
; 0.741  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.513      ;
; 0.741  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.513      ;
; 0.741  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.513      ;
; 0.741  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.316      ; 1.513      ;
; 0.849  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.068      ;
; 0.874  ; q0_2hz_sync                            ; two_hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.093      ;
; 0.943  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.162      ;
; 0.969  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.188      ;
; 1.042  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.261      ;
; 1.090  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.309      ;
; 1.427  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.646      ;
; 1.427  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.646      ;
; 1.427  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.646      ;
; 1.427  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.646      ;
; 1.436  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.655      ;
; 1.794  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.013      ;
; 1.842  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.061      ;
; 2.002  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.221      ;
; 2.865  ; count_2hz[1]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 2.934      ;
; 2.970  ; count_2hz[2]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.039      ;
; 3.044  ; count_2hz[0]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.113      ;
; 3.047  ; count_2hz[3]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.116      ;
; 3.122  ; count_2hz[4]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.191      ;
; 3.226  ; count_2hz[6]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.295      ;
; 3.304  ; count_2hz[5]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.373      ;
; 3.453  ; count_2hz[7]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.142      ; 3.522      ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                     ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                               ; To Node                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.358 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.358 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.577      ;
; 0.361 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.580      ;
; 0.372 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.592      ;
; 0.372 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.592      ;
; 0.372 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.592      ;
; 0.373 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.373 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.593      ;
; 0.374 ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.594      ;
; 0.375 ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.594      ;
; 0.375 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.595      ;
; 0.377 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.596      ;
; 0.387 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.606      ;
; 0.390 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.609      ;
; 0.391 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.610      ;
; 0.415 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.634      ;
; 0.476 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.695      ;
; 0.515 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.735      ;
; 0.516 ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.735      ;
; 0.516 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.735      ;
; 0.516 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.736      ;
; 0.517 ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.736      ;
; 0.517 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 0.737      ;
; 0.522 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.741      ;
; 0.523 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.742      ;
; 0.524 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.743      ;
; 0.525 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.744      ;
; 0.525 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.744      ;
; 0.541 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.760      ;
; 0.580 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.799      ;
; 0.599 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.818      ;
; 0.617 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.836      ;
; 0.638 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.857      ;
; 0.678 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.897      ;
; 0.699 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.918      ;
; 0.710 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.929      ;
; 0.715 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 0.934      ;
; 0.791 ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.026      ;
; 0.799 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.018      ;
; 0.878 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.098      ;
; 0.879 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.098      ;
; 0.883 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.102      ;
; 0.883 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.102      ;
; 0.884 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.103      ;
; 0.913 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.132      ;
; 0.941 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.063      ; 1.161      ;
; 0.979 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.198      ;
; 0.993 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.212      ;
; 1.022 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.241      ;
; 1.026 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.245      ;
; 1.038 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.257      ;
; 1.040 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.259      ;
; 1.046 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.265      ;
; 1.077 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.296      ;
; 1.095 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.314      ;
; 1.096 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.315      ;
; 1.122 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.341      ;
; 1.123 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.342      ;
; 1.206 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.425      ;
; 1.282 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.501      ;
; 1.282 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.501      ;
; 1.293 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.512      ;
; 1.426 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.645      ;
; 1.446 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.665      ;
; 1.446 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.062      ; 1.665      ;
; 1.606 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.841      ;
; 1.606 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.841      ;
; 1.606 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.841      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.650 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.885      ;
; 1.706 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.941      ;
; 1.706 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.941      ;
; 1.706 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.941      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.814 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.049      ;
; 1.824 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.059      ;
; 1.824 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.059      ;
; 1.824 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.059      ;
; 1.933 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.168      ;
; 1.933 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.168      ;
; 1.933 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 2.168      ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                       ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.358 ; start_send_ps            ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
; 0.362 ; adc_data_rdy_stretch     ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
; 0.374 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
; 0.374 ; q1_sync                  ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
; 0.384 ; serial_bit_cntr_ps.BIT_9 ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.603      ;
; 0.404 ; q_stretch                ; q0_sync                  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.056     ; 0.595      ;
; 0.421 ; uart_main_ps.CHAR_6      ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.640      ;
; 0.481 ; q0_sync                  ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.699      ;
; 0.516 ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.735      ;
; 0.517 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.736      ;
; 0.517 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.736      ;
; 0.525 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.744      ;
; 0.528 ; adc_data_rdy_stretch     ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.746      ;
; 0.538 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.757      ;
; 0.542 ; uart_main_ps.CHAR_4      ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.761      ;
; 0.551 ; uart_main_ps.CHAR_3      ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.770      ;
; 0.551 ; uart_main_ps.CHAR_2      ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.770      ;
; 0.553 ; uart_main_ps.CHAR_6      ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.772      ;
; 0.647 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.866      ;
; 0.660 ; uart_main_ps.CHAR_0      ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.879      ;
; 0.673 ; uart_main_ps.CHAR_1      ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.892      ;
; 0.682 ; uart_main_ps.CHAR_5      ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.901      ;
; 0.692 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.911      ;
; 0.733 ; adc_data_rdy_stretch     ; q0_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.951      ;
; 0.794 ; serial_bit_cntr_ps.BIT_8 ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.013      ;
; 0.986 ; adc_data_rdy_stretch     ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.208      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.062 ; start_send_ps            ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.281      ;
; 1.566 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.785      ;
; 1.566 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.785      ;
; 1.566 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.785      ;
; 1.569 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.788      ;
; 1.569 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.788      ;
; 1.569 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.788      ;
; 1.569 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.788      ;
; 1.815 ; start_send_ps            ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.034      ;
; 1.815 ; start_send_ps            ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.034      ;
; 1.815 ; start_send_ps            ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.034      ;
; 1.827 ; start_send_ps            ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.046      ;
; 1.827 ; start_send_ps            ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.046      ;
; 1.827 ; start_send_ps            ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.046      ;
; 1.827 ; start_send_ps            ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.046      ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'digit_clk'                                                                         ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node       ; To Node         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; 0.404 ; digit_seq_ps[1] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 0.622      ;
; 0.652 ; digit_seq_ps[2] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 0.870      ;
; 0.862 ; digit_seq_ps[1] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 1.080      ;
; 0.890 ; digit_seq_ps[1] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 1.108      ;
; 0.961 ; digit_seq_ps[0] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 1.179      ;
; 0.968 ; digit_seq_ps[0] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 1.186      ;
; 1.088 ; digit_seq_ps[2] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 1.306      ;
; 1.136 ; digit_seq_ps[2] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.061      ; 1.354      ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'adc_control:adc_control_0|s_clk'                                                                                                                                                ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; Slack ; From Node                              ; To Node             ; Launch Clock                                               ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; 0.414 ; adc_sr_data_out[10]                    ; adc_sr_data_out[11] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.634      ;
; 0.535 ; adc_sr_data_out[6]                     ; adc_sr_data_out[7]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.755      ;
; 0.536 ; adc_sr_data_out[9]                     ; adc_sr_data_out[10] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.756      ;
; 0.537 ; adc_sr_data_out[7]                     ; adc_sr_data_out[8]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.757      ;
; 0.538 ; adc_sr_data_out[1]                     ; adc_sr_data_out[2]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.758      ;
; 0.557 ; adc_sr_data_out[5]                     ; adc_sr_data_out[6]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.777      ;
; 0.557 ; adc_sr_data_out[0]                     ; adc_sr_data_out[1]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.777      ;
; 0.678 ; adc_sr_data_out[3]                     ; adc_sr_data_out[4]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.898      ;
; 0.679 ; adc_sr_data_out[8]                     ; adc_sr_data_out[9]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.899      ;
; 0.693 ; adc_sr_data_out[4]                     ; adc_sr_data_out[5]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.913      ;
; 0.715 ; adc_sr_data_out[2]                     ; adc_sr_data_out[3]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.063      ; 0.935      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
; 1.169 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 3.027      ; 4.433      ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'adc_control:adc_control_0|adc_ps.STOP'                                                                                                                 ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node   ; Launch Clock                                               ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; -0.832 ; adc_data_rdy_stretch ; q_stretch ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 1.000        ; 0.056      ; 1.813      ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'adc_control:adc_control_0|adc_ps.STOP'                                                                                                                 ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node   ; Launch Clock                                               ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; 0.925 ; adc_data_rdy_stretch ; q_stretch ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 0.000        ; 0.529      ; 1.671      ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+


-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 664.338 ns




+---------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                           ;
+-------------+-----------------+------------------------------------------------------------+------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name                                                 ; Note                                           ;
+-------------+-----------------+------------------------------------------------------------+------------------------------------------------+
; 447.43 MHz  ; 447.43 MHz      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 481.0 MHz   ; 481.0 MHz       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ;                                                ;
; 521.65 MHz  ; 500.0 MHz       ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; limit due to minimum period restriction (tmin) ;
; 626.17 MHz  ; 500.0 MHz       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; limit due to minimum period restriction (tmin) ;
; 723.59 MHz  ; 500.0 MHz       ; digit_clk                                                  ; limit due to minimum period restriction (tmin) ;
; 1022.49 MHz ; 500.0 MHz       ; adc_control:adc_control_0|s_clk                            ; limit due to minimum period restriction (tmin) ;
+-------------+-----------------+------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                    ;
+------------------------------------------------------------+----------+---------------+
; Clock                                                      ; Slack    ; End Point TNS ;
+------------------------------------------------------------+----------+---------------+
; adc_control:adc_control_0|s_clk                            ; -2.066   ; -24.792       ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -1.208   ; -8.590        ;
; digit_clk                                                  ; -0.382   ; -0.730        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.371   ; -2.968        ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.086   ; -0.086        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6508.337 ; 0.000         ;
+------------------------------------------------------------+----------+---------------+


+-------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                   ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.265 ; -0.265        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.259 ; -0.259        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.312  ; 0.000         ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.313  ; 0.000         ;
; digit_clk                                                  ; 0.359  ; 0.000         ;
; adc_control:adc_control_0|s_clk                            ; 0.375  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                          ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; adc_control:adc_control_0|adc_ps.STOP ; -0.685 ; -0.685        ;
+---------------------------------------+--------+---------------+


+---------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                          ;
+---------------------------------------+-------+---------------+
; Clock                                 ; Slack ; End Point TNS ;
+---------------------------------------+-------+---------------+
; adc_control:adc_control_0|adc_ps.STOP ; 0.888 ; 0.000         ;
+---------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                        ;
+------------------------------------------------------------+------------+---------------+
; Clock                                                      ; Slack      ; End Point TNS ;
+------------------------------------------------------------+------------+---------------+
; adc_control:adc_control_0|s_clk                            ; -1.000     ; -12.000       ;
; digit_clk                                                  ; -1.000     ; -3.000        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; -1.000     ; -1.000        ;
; inclk0_sig                                                 ; 9.817      ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 166.412    ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 3254.951   ; 0.000         ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 52083.081  ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 124999.743 ; 0.000         ;
+------------------------------------------------------------+------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'adc_control:adc_control_0|s_clk'                                                                                                                                                 ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node             ; Launch Clock                                               ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.066 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.163      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; -2.048 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 2.181      ; 4.145      ;
; 0.022  ; adc_sr_data_out[2]                     ; adc_sr_data_out[3]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.918      ;
; 0.041  ; adc_sr_data_out[4]                     ; adc_sr_data_out[5]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.899      ;
; 0.056  ; adc_sr_data_out[3]                     ; adc_sr_data_out[4]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.884      ;
; 0.058  ; adc_sr_data_out[8]                     ; adc_sr_data_out[9]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.882      ;
; 0.145  ; adc_sr_data_out[5]                     ; adc_sr_data_out[6]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.795      ;
; 0.152  ; adc_sr_data_out[0]                     ; adc_sr_data_out[1]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.788      ;
; 0.170  ; adc_sr_data_out[1]                     ; adc_sr_data_out[2]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.770      ;
; 0.172  ; adc_sr_data_out[7]                     ; adc_sr_data_out[8]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.768      ;
; 0.173  ; adc_sr_data_out[9]                     ; adc_sr_data_out[10] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.767      ;
; 0.175  ; adc_sr_data_out[6]                     ; adc_sr_data_out[7]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.765      ;
; 0.284  ; adc_sr_data_out[10]                    ; adc_sr_data_out[11] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.055     ; 0.656      ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                     ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                              ; To Node                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -1.208  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.314      ;
; -1.208  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.314      ;
; -1.208  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.314      ;
; -1.208  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.314      ;
; -1.162  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.268      ;
; -1.162  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.268      ;
; -1.162  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.268      ;
; -1.162  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.268      ;
; -1.141  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.247      ;
; -1.073  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.179      ;
; -1.067  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.183      ;
; -1.061  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.167      ;
; -1.052  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.168      ;
; -1.015  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 1.121      ;
; -0.477  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 0.583      ;
; -0.456  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.010     ; 0.562      ;
; 329.683 ; count_2hz[7]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 3.495      ;
; 329.810 ; count_2hz[5]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 3.368      ;
; 329.887 ; count_2hz[6]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 3.291      ;
; 330.017 ; count_2hz[4]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 3.161      ;
; 330.106 ; count_2hz[0]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 3.072      ;
; 330.118 ; count_2hz[3]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 3.060      ;
; 330.196 ; count_2hz[2]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 2.982      ;
; 330.321 ; count_2hz[1]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.150     ; 2.857      ;
; 331.098 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 2.175      ;
; 331.268 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 2.005      ;
; 331.271 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 2.002      ;
; 331.673 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.600      ;
; 331.738 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.535      ;
; 331.738 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.535      ;
; 331.738 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.535      ;
; 331.738 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.535      ;
; 331.971 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.302      ;
; 331.974 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.299      ;
; 332.097 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.176      ;
; 332.111 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.162      ;
; 332.209 ; q0_2hz_sync                            ; two_hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.064      ;
; 332.225 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 1.048      ;
; 332.281 ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.992      ;
; 332.286 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.987      ;
; 332.387 ; two_hz_sync                            ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.886      ;
; 332.394 ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.879      ;
; 332.408 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.865      ;
; 332.412 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.861      ;
; 332.420 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.853      ;
; 332.499 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.774      ;
; 332.500 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.773      ;
; 332.504 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.769      ;
; 332.523 ; two_hz_sync                            ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.750      ;
; 332.613 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.660      ;
; 332.641 ; button_pulse_ps.PULSE                  ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.632      ;
; 332.646 ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.627      ;
; 332.652 ; button_pulse_ps.DETECT                 ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.621      ;
; 332.690 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.583      ;
; 332.690 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.583      ;
; 332.690 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.583      ;
; 332.711 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.562      ;
; 332.711 ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.055     ; 0.562      ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'digit_clk'                                                                          ;
+--------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node       ; To Node         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; -0.382 ; digit_seq_ps[2] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 1.322      ;
; -0.348 ; digit_seq_ps[2] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 1.288      ;
; -0.262 ; digit_seq_ps[0] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 1.202      ;
; -0.259 ; digit_seq_ps[0] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 1.199      ;
; -0.139 ; digit_seq_ps[1] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 1.079      ;
; -0.136 ; digit_seq_ps[1] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 1.076      ;
; 0.027  ; digit_seq_ps[2] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 0.913      ;
; 0.287  ; digit_seq_ps[1] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 1.000        ; -0.055     ; 0.653      ;
+--------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                          ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack      ; From Node       ; To Node         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.371     ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; -0.371     ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.988      ;
; 0.055      ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; 0.002      ; 0.562      ;
; 0.163      ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.163      ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.954      ;
; 0.534      ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; 0.002      ; 0.583      ;
; 249998.403 ; count_2hz[1]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.536      ;
; 249998.404 ; count_2hz[0]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.535      ;
; 249998.421 ; count_2hz[1]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.518      ;
; 249998.462 ; count_2hz[0]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.477      ;
; 249998.497 ; count_2hz[3]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.442      ;
; 249998.501 ; count_2hz[2]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.438      ;
; 249998.503 ; count_2hz[1]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.436      ;
; 249998.504 ; count_2hz[0]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.435      ;
; 249998.515 ; count_2hz[3]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.424      ;
; 249998.521 ; count_2hz[1]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.418      ;
; 249998.562 ; count_2hz[0]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.377      ;
; 249998.568 ; count_2hz[2]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.371      ;
; 249998.597 ; count_2hz[5]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.342      ;
; 249998.597 ; count_2hz[3]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.342      ;
; 249998.601 ; count_2hz[4]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.338      ;
; 249998.601 ; count_2hz[2]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.338      ;
; 249998.603 ; count_2hz[1]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.336      ;
; 249998.604 ; count_2hz[0]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.335      ;
; 249998.615 ; count_2hz[5]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.324      ;
; 249998.615 ; count_2hz[3]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.324      ;
; 249998.621 ; count_2hz[1]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.318      ;
; 249998.662 ; count_2hz[0]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.277      ;
; 249998.668 ; count_2hz[2]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.271      ;
; 249998.669 ; count_2hz[4]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.270      ;
; 249998.701 ; count_2hz[4]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.238      ;
; 249998.701 ; count_2hz[2]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.238      ;
; 249998.704 ; count_2hz[0]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.235      ;
; 249998.706 ; count_2hz[6]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 1.233      ;
; 249999.050 ; count_2hz[0]    ; count_2hz[0]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.889      ;
; 249999.054 ; count_2hz[6]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.885      ;
; 249999.056 ; count_2hz[2]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.883      ;
; 249999.057 ; count_2hz[4]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.882      ;
; 249999.065 ; count_2hz[5]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.874      ;
; 249999.065 ; count_2hz[3]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.874      ;
; 249999.069 ; count_2hz[1]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.870      ;
; 249999.094 ; debounce_cnt[0] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.845      ;
; 249999.302 ; count_2hz[7]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.637      ;
; 249999.305 ; debounce_cnt[0] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.634      ;
; 249999.321 ; debounce_cnt[1] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.618      ;
; 249999.356 ; debounce_cnt[0] ; debounce_cnt[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.583      ;
; 249999.356 ; debounce_cnt[1] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.056     ; 0.583      ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                            ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack      ; From Node                ; To Node                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.086     ; q_stretch                ; q0_sync                  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 1.000        ; -0.429     ; 0.612      ;
; 104164.749 ; start_send_ps            ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.858      ;
; 104164.749 ; start_send_ps            ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.858      ;
; 104164.749 ; start_send_ps            ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.858      ;
; 104164.749 ; start_send_ps            ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.858      ;
; 104164.752 ; start_send_ps            ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.855      ;
; 104164.752 ; start_send_ps            ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.855      ;
; 104164.752 ; start_send_ps            ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.855      ;
; 104164.926 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.680      ;
; 104164.926 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.680      ;
; 104164.926 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.680      ;
; 104164.926 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.680      ;
; 104164.940 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.666      ;
; 104164.940 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.666      ;
; 104164.940 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.666      ;
; 104165.336 ; adc_data_rdy_stretch     ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.051     ; 1.274      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.481 ; start_send_ps            ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 1.126      ;
; 104165.597 ; serial_bit_cntr_ps.BIT_8 ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 1.009      ;
; 104165.632 ; adc_data_rdy_stretch     ; q0_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.975      ;
; 104165.689 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.917      ;
; 104165.714 ; uart_main_ps.CHAR_5      ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.893      ;
; 104165.724 ; uart_main_ps.CHAR_1      ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.882      ;
; 104165.745 ; uart_main_ps.CHAR_0      ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.861      ;
; 104165.748 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.858      ;
; 104165.822 ; uart_main_ps.CHAR_3      ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.785      ;
; 104165.822 ; uart_main_ps.CHAR_2      ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.785      ;
; 104165.831 ; uart_main_ps.CHAR_4      ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.776      ;
; 104165.838 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.768      ;
; 104165.843 ; uart_main_ps.CHAR_6      ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.763      ;
; 104165.844 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.762      ;
; 104165.846 ; adc_data_rdy_stretch     ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.761      ;
; 104165.857 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.749      ;
; 104165.858 ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.748      ;
; 104165.858 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.748      ;
; 104165.871 ; q0_sync                  ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.736      ;
; 104165.930 ; uart_main_ps.CHAR_6      ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.676      ;
; 104165.968 ; serial_bit_cntr_ps.BIT_9 ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.638      ;
; 104165.995 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.611      ;
; 104165.996 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.055     ; 0.610      ;
; 104165.999 ; q1_sync                  ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.608      ;
; 104166.024 ; start_send_ps            ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.583      ;
; 104166.024 ; adc_data_rdy_stretch     ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.054     ; 0.583      ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                        ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack    ; From Node                                               ; To Node                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 6508.337 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 2.004      ;
; 6508.337 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 2.004      ;
; 6508.337 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 2.004      ;
; 6508.399 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.942      ;
; 6508.399 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.942      ;
; 6508.399 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.942      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.413 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.928      ;
; 6508.546 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.795      ;
; 6508.546 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.795      ;
; 6508.546 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.795      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.594 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.747      ;
; 6508.668 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.673      ;
; 6508.668 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.673      ;
; 6508.668 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.673      ;
; 6508.749 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.607      ;
; 6508.786 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.570      ;
; 6508.786 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.570      ;
; 6508.839 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.517      ;
; 6508.854 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.502      ;
; 6508.879 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.477      ;
; 6508.901 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.455      ;
; 6508.903 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.453      ;
; 6508.922 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.434      ;
; 6508.946 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.410      ;
; 6508.967 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.389      ;
; 6508.967 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.389      ;
; 6508.973 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.383      ;
; 6508.974 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.382      ;
; 6509.032 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.324      ;
; 6509.048 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.308      ;
; 6509.067 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.289      ;
; 6509.085 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.271      ;
; 6509.086 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.270      ;
; 6509.090 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.266      ;
; 6509.147 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.209      ;
; 6509.154 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.202      ;
; 6509.155 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.201      ;
; 6509.170 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.186      ;
; 6509.198 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.158      ;
; 6509.222 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.134      ;
; 6509.224 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.132      ;
; 6509.249 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.107      ;
; 6509.299 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 1.057      ;
; 6509.321 ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.070     ; 1.020      ;
; 6509.388 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.968      ;
; 6509.392 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.964      ;
; 6509.421 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.935      ;
; 6509.434 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.922      ;
; 6509.445 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.911      ;
; 6509.445 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.911      ;
; 6509.457 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.899      ;
; 6509.475 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.881      ;
; 6509.595 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.761      ;
; 6509.597 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.758      ;
; 6509.597 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.758      ;
; 6509.599 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.756      ;
; 6509.599 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.756      ;
; 6509.605 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.751      ;
; 6509.607 ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.748      ;
; 6509.607 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.749      ;
; 6509.608 ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.747      ;
; 6509.608 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.748      ;
; 6509.609 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.747      ;
; 6509.646 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.710      ;
; 6509.715 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.641      ;
; 6509.724 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.632      ;
; 6509.724 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.632      ;
; 6509.727 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.629      ;
; 6509.744 ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.611      ;
; 6509.744 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.612      ;
; 6509.745 ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.610      ;
; 6509.745 ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.056     ; 0.610      ;
; 6509.745 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.611      ;
; 6509.745 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.611      ;
; 6509.747 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.609      ;
; 6509.747 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.609      ;
; 6509.747 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.609      ;
; 6509.747 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.609      ;
; 6509.748 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.608      ;
; 6509.773 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.583      ;
; 6509.773 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.583      ;
; 6509.773 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.583      ;
; 6509.794 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.562      ;
; 6509.794 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.562      ;
; 6509.794 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.562      ;
; 6509.794 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.562      ;
; 6509.794 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.055     ; 0.562      ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                       ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node       ; To Node         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.265 ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 0.518      ;
; 0.228  ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 0.511      ;
; 0.236  ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.236  ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.359      ; 1.019      ;
; 0.311  ; debounce_cnt[1] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.511      ;
; 0.319  ; debounce_cnt[0] ; debounce_cnt[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.519      ;
; 0.328  ; debounce_cnt[1] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.528      ;
; 0.337  ; debounce_cnt[0] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.537      ;
; 0.346  ; count_2hz[7]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.546      ;
; 0.500  ; count_2hz[6]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.700      ;
; 0.500  ; count_2hz[1]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.700      ;
; 0.502  ; count_2hz[5]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.702      ;
; 0.502  ; count_2hz[3]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.702      ;
; 0.505  ; count_2hz[4]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.705      ;
; 0.505  ; count_2hz[2]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.705      ;
; 0.505  ; debounce_cnt[0] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.705      ;
; 0.516  ; count_2hz[0]    ; count_2hz[0]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.716      ;
; 0.744  ; count_2hz[1]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.944      ;
; 0.747  ; count_2hz[5]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.947      ;
; 0.747  ; count_2hz[3]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.947      ;
; 0.749  ; count_2hz[6]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.949      ;
; 0.750  ; count_2hz[0]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.950      ;
; 0.754  ; count_2hz[4]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.954      ;
; 0.754  ; count_2hz[2]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.954      ;
; 0.757  ; count_2hz[0]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.957      ;
; 0.761  ; count_2hz[4]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.961      ;
; 0.761  ; count_2hz[2]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 0.961      ;
; 0.768  ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.768  ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.359      ; 1.051      ;
; 0.833  ; count_2hz[1]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.033      ;
; 0.836  ; count_2hz[5]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.036      ;
; 0.836  ; count_2hz[3]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.036      ;
; 0.840  ; count_2hz[1]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.040      ;
; 0.843  ; count_2hz[3]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.043      ;
; 0.846  ; count_2hz[0]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.046      ;
; 0.850  ; count_2hz[4]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.050      ;
; 0.850  ; count_2hz[2]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.050      ;
; 0.853  ; count_2hz[0]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.053      ;
; 0.857  ; count_2hz[2]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.057      ;
; 0.929  ; count_2hz[1]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.129      ;
; 0.932  ; count_2hz[3]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.132      ;
; 0.936  ; count_2hz[1]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.136      ;
; 0.942  ; count_2hz[0]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.142      ;
; 0.946  ; count_2hz[2]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.146      ;
; 0.949  ; count_2hz[0]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.149      ;
; 1.025  ; count_2hz[1]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.225      ;
; 1.038  ; count_2hz[0]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.056      ; 1.238      ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                     ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.259 ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 0.511      ;
; -0.252 ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 0.518      ;
; 0.295  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.055      ;
; 0.303  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.073      ;
; 0.312  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
; 0.315  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.075      ;
; 0.331  ; button_pulse_ps.DETECT                 ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.530      ;
; 0.339  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.109      ;
; 0.349  ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.548      ;
; 0.351  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.121      ;
; 0.353  ; button_pulse_ps.PULSE                  ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.552      ;
; 0.360  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.559      ;
; 0.423  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.193      ;
; 0.442  ; two_hz_sync                            ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.641      ;
; 0.495  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.694      ;
; 0.498  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.697      ;
; 0.498  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.697      ;
; 0.514  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.713      ;
; 0.517  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.716      ;
; 0.526  ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.725      ;
; 0.529  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.728      ;
; 0.534  ; two_hz_sync                            ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.733      ;
; 0.551  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.321      ;
; 0.551  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.321      ;
; 0.551  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.321      ;
; 0.551  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.321      ;
; 0.595  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.365      ;
; 0.595  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.365      ;
; 0.595  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.365      ;
; 0.595  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.346      ; 1.365      ;
; 0.661  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.860      ;
; 0.665  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.864      ;
; 0.786  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.985      ;
; 0.795  ; q0_2hz_sync                            ; two_hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.994      ;
; 0.851  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.050      ;
; 0.890  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.089      ;
; 0.950  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.149      ;
; 1.008  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.207      ;
; 1.288  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.487      ;
; 1.288  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.487      ;
; 1.288  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.487      ;
; 1.288  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.487      ;
; 1.296  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.495      ;
; 1.634  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.833      ;
; 1.692  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.891      ;
; 1.842  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 2.041      ;
; 2.686  ; count_2hz[1]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 2.725      ;
; 2.776  ; count_2hz[2]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 2.815      ;
; 2.843  ; count_2hz[0]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 2.882      ;
; 2.844  ; count_2hz[3]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 2.883      ;
; 2.929  ; count_2hz[4]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 2.968      ;
; 3.022  ; count_2hz[6]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 3.061      ;
; 3.089  ; count_2hz[5]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 3.128      ;
; 3.233  ; count_2hz[7]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.125      ; 3.272      ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                      ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                               ; To Node                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.312 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.312 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.511      ;
; 0.320 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.519      ;
; 0.336 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.535      ;
; 0.338 ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.538      ;
; 0.338 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.537      ;
; 0.339 ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.539      ;
; 0.339 ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.539      ;
; 0.339 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.538      ;
; 0.339 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.538      ;
; 0.340 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.539      ;
; 0.341 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.540      ;
; 0.345 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.544      ;
; 0.355 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.554      ;
; 0.355 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.554      ;
; 0.372 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.571      ;
; 0.422 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.621      ;
; 0.456 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.655      ;
; 0.464 ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.664      ;
; 0.465 ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.665      ;
; 0.465 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.664      ;
; 0.466 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.665      ;
; 0.467 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.666      ;
; 0.470 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.670      ;
; 0.470 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.670      ;
; 0.471 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.671      ;
; 0.471 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.056      ; 0.671      ;
; 0.476 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.675      ;
; 0.500 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.699      ;
; 0.521 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.720      ;
; 0.539 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.738      ;
; 0.555 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.754      ;
; 0.570 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.769      ;
; 0.617 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.816      ;
; 0.628 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.827      ;
; 0.649 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.848      ;
; 0.653 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.852      ;
; 0.716 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.915      ;
; 0.729 ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 0.942      ;
; 0.795 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.994      ;
; 0.796 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.995      ;
; 0.797 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.996      ;
; 0.800 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 0.999      ;
; 0.811 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.010      ;
; 0.826 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.025      ;
; 0.861 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.060      ;
; 0.883 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.082      ;
; 0.893 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.092      ;
; 0.901 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.100      ;
; 0.924 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.123      ;
; 0.925 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.124      ;
; 0.930 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.129      ;
; 0.939 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.138      ;
; 0.969 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.168      ;
; 0.984 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.183      ;
; 0.985 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.184      ;
; 1.003 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.202      ;
; 1.004 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.203      ;
; 1.097 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.296      ;
; 1.151 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.350      ;
; 1.162 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.361      ;
; 1.162 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.361      ;
; 1.304 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.503      ;
; 1.305 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.504      ;
; 1.305 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.055      ; 1.504      ;
; 1.472 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.685      ;
; 1.472 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.685      ;
; 1.472 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.685      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.514 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.727      ;
; 1.560 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.773      ;
; 1.560 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.773      ;
; 1.560 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.773      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.657 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.870      ;
; 1.665 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.878      ;
; 1.665 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.878      ;
; 1.665 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.878      ;
; 1.774 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.987      ;
; 1.774 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.987      ;
; 1.774 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.987      ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.313 ; start_send_ps            ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
; 0.317 ; q_stretch                ; q0_sync                  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.011     ; 0.540      ;
; 0.321 ; adc_data_rdy_stretch     ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
; 0.339 ; q1_sync                  ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.537      ;
; 0.340 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
; 0.340 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
; 0.343 ; serial_bit_cntr_ps.BIT_9 ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.542      ;
; 0.373 ; uart_main_ps.CHAR_6      ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.572      ;
; 0.434 ; q0_sync                  ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.632      ;
; 0.465 ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.664      ;
; 0.466 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.665      ;
; 0.467 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.666      ;
; 0.474 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.673      ;
; 0.483 ; adc_data_rdy_stretch     ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.681      ;
; 0.485 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.684      ;
; 0.490 ; uart_main_ps.CHAR_4      ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.688      ;
; 0.495 ; uart_main_ps.CHAR_2      ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.693      ;
; 0.497 ; uart_main_ps.CHAR_3      ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.695      ;
; 0.511 ; uart_main_ps.CHAR_6      ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.709      ;
; 0.583 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.782      ;
; 0.601 ; uart_main_ps.CHAR_5      ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.800      ;
; 0.603 ; uart_main_ps.CHAR_0      ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.802      ;
; 0.619 ; uart_main_ps.CHAR_1      ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.817      ;
; 0.635 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.834      ;
; 0.670 ; adc_data_rdy_stretch     ; q0_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.868      ;
; 0.724 ; serial_bit_cntr_ps.BIT_8 ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.922      ;
; 0.910 ; adc_data_rdy_stretch     ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.057      ; 1.111      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 0.970 ; start_send_ps            ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.169      ;
; 1.418 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.617      ;
; 1.418 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.617      ;
; 1.418 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.617      ;
; 1.422 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.620      ;
; 1.422 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.620      ;
; 1.422 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.620      ;
; 1.422 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.620      ;
; 1.667 ; start_send_ps            ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.866      ;
; 1.667 ; start_send_ps            ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.866      ;
; 1.667 ; start_send_ps            ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 1.866      ;
; 1.681 ; start_send_ps            ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.879      ;
; 1.681 ; start_send_ps            ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.879      ;
; 1.681 ; start_send_ps            ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.879      ;
; 1.681 ; start_send_ps            ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 1.879      ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'digit_clk'                                                                          ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node       ; To Node         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; 0.359 ; digit_seq_ps[1] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 0.558      ;
; 0.580 ; digit_seq_ps[2] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 0.779      ;
; 0.780 ; digit_seq_ps[1] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 0.979      ;
; 0.800 ; digit_seq_ps[1] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 0.999      ;
; 0.866 ; digit_seq_ps[0] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 1.065      ;
; 0.872 ; digit_seq_ps[0] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 1.071      ;
; 0.976 ; digit_seq_ps[2] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 1.175      ;
; 1.019 ; digit_seq_ps[2] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.055      ; 1.218      ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'adc_control:adc_control_0|s_clk'                                                                                                                                                 ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; Slack ; From Node                              ; To Node             ; Launch Clock                                               ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; 0.375 ; adc_sr_data_out[10]                    ; adc_sr_data_out[11] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.574      ;
; 0.483 ; adc_sr_data_out[6]                     ; adc_sr_data_out[7]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.682      ;
; 0.484 ; adc_sr_data_out[9]                     ; adc_sr_data_out[10] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.683      ;
; 0.485 ; adc_sr_data_out[7]                     ; adc_sr_data_out[8]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.684      ;
; 0.486 ; adc_sr_data_out[1]                     ; adc_sr_data_out[2]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.685      ;
; 0.499 ; adc_sr_data_out[5]                     ; adc_sr_data_out[6]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.698      ;
; 0.503 ; adc_sr_data_out[0]                     ; adc_sr_data_out[1]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.702      ;
; 0.616 ; adc_sr_data_out[3]                     ; adc_sr_data_out[4]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.815      ;
; 0.623 ; adc_sr_data_out[8]                     ; adc_sr_data_out[9]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.822      ;
; 0.633 ; adc_sr_data_out[4]                     ; adc_sr_data_out[5]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.832      ;
; 0.641 ; adc_sr_data_out[2]                     ; adc_sr_data_out[3]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.055      ; 0.840      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.126 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.008      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
; 1.157 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 2.658      ; 4.039      ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'adc_control:adc_control_0|adc_ps.STOP'                                                                                                                  ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node   ; Launch Clock                                               ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; -0.685 ; adc_data_rdy_stretch ; q_stretch ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 1.000        ; 0.011      ; 1.621      ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'adc_control:adc_control_0|adc_ps.STOP'                                                                                                                  ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node   ; Launch Clock                                               ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; 0.888 ; adc_data_rdy_stretch ; q_stretch ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 0.000        ; 0.429      ; 1.521      ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+


----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 664.596 ns




+---------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                    ;
+------------------------------------------------------------+----------+---------------+
; Clock                                                      ; Slack    ; End Point TNS ;
+------------------------------------------------------------+----------+---------------+
; adc_control:adc_control_0|s_clk                            ; -1.341   ; -16.092       ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.882   ; -6.493        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.171   ; -1.368        ;
; digit_clk                                                  ; 0.150    ; 0.000         ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.249    ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6509.079 ; 0.000         ;
+------------------------------------------------------------+----------+---------------+


+-------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                   ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.116 ; -0.116        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.106 ; -0.106        ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.183  ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.187  ; 0.000         ;
; digit_clk                                                  ; 0.216  ; 0.000         ;
; adc_control:adc_control_0|s_clk                            ; 0.217  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                          ;
+---------------------------------------+--------+---------------+
; Clock                                 ; Slack  ; End Point TNS ;
+---------------------------------------+--------+---------------+
; adc_control:adc_control_0|adc_ps.STOP ; -0.066 ; -0.066        ;
+---------------------------------------+--------+---------------+


+---------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                          ;
+---------------------------------------+-------+---------------+
; Clock                                 ; Slack ; End Point TNS ;
+---------------------------------------+-------+---------------+
; adc_control:adc_control_0|adc_ps.STOP ; 0.437 ; 0.000         ;
+---------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                        ;
+------------------------------------------------------------+------------+---------------+
; Clock                                                      ; Slack      ; End Point TNS ;
+------------------------------------------------------------+------------+---------------+
; adc_control:adc_control_0|s_clk                            ; -1.000     ; -12.000       ;
; digit_clk                                                  ; -1.000     ; -3.000        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; -1.000     ; -1.000        ;
; inclk0_sig                                                 ; 9.587      ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 166.448    ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 3254.990   ; 0.000         ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 52083.117  ; 0.000         ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 124999.782 ; 0.000         ;
+------------------------------------------------------------+------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'adc_control:adc_control_0|s_clk'                                                                                                                                                 ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node             ; Launch Clock                                               ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.341 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.777      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; -1.296 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.001        ; 1.528      ; 2.732      ;
; 0.393  ; adc_sr_data_out[2]                     ; adc_sr_data_out[3]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.558      ;
; 0.410  ; adc_sr_data_out[4]                     ; adc_sr_data_out[5]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.541      ;
; 0.418  ; adc_sr_data_out[3]                     ; adc_sr_data_out[4]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.533      ;
; 0.421  ; adc_sr_data_out[8]                     ; adc_sr_data_out[9]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.530      ;
; 0.480  ; adc_sr_data_out[5]                     ; adc_sr_data_out[6]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.471      ;
; 0.486  ; adc_sr_data_out[0]                     ; adc_sr_data_out[1]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.465      ;
; 0.497  ; adc_sr_data_out[1]                     ; adc_sr_data_out[2]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.454      ;
; 0.499  ; adc_sr_data_out[9]                     ; adc_sr_data_out[10] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.452      ;
; 0.499  ; adc_sr_data_out[7]                     ; adc_sr_data_out[8]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.452      ;
; 0.502  ; adc_sr_data_out[6]                     ; adc_sr_data_out[7]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.449      ;
; 0.548  ; adc_sr_data_out[10]                    ; adc_sr_data_out[11] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 1.000        ; -0.036     ; 0.403      ;
+--------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                     ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                              ; To Node                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.882  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.796      ;
; -0.882  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.796      ;
; -0.882  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.796      ;
; -0.882  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.796      ;
; -0.862  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.776      ;
; -0.835  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.749      ;
; -0.835  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.749      ;
; -0.835  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.749      ;
; -0.835  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.749      ;
; -0.834  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.748      ;
; -0.824  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.748      ;
; -0.780  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.694      ;
; -0.764  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.688      ;
; -0.730  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.644      ;
; -0.445  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.359      ;
; -0.436  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.001        ; -0.119     ; 0.350      ;
; 330.872 ; count_2hz[7]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 2.346      ;
; 330.955 ; count_2hz[5]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 2.263      ;
; 331.016 ; count_2hz[6]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 2.202      ;
; 331.090 ; count_2hz[4]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 2.128      ;
; 331.158 ; count_2hz[0]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 2.060      ;
; 331.162 ; count_2hz[3]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 2.056      ;
; 331.224 ; count_2hz[2]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 1.994      ;
; 331.296 ; count_2hz[1]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.102     ; 1.922      ;
; 331.840 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 1.444      ;
; 332.011 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 1.273      ;
; 332.028 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 1.256      ;
; 332.334 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.950      ;
; 332.343 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.941      ;
; 332.343 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.941      ;
; 332.343 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.941      ;
; 332.343 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.941      ;
; 332.466 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.818      ;
; 332.483 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.801      ;
; 332.558 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.726      ;
; 332.565 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.719      ;
; 332.630 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.654      ;
; 332.634 ; q0_2hz_sync                            ; two_hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.650      ;
; 332.663 ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.621      ;
; 332.666 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.618      ;
; 332.737 ; two_hz_sync                            ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.547      ;
; 332.742 ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.542      ;
; 332.749 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.535      ;
; 332.752 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.532      ;
; 332.753 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.531      ;
; 332.802 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.482      ;
; 332.802 ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.482      ;
; 332.809 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.475      ;
; 332.830 ; two_hz_sync                            ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.454      ;
; 332.884 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.400      ;
; 332.896 ; button_pulse_ps.PULSE                  ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.388      ;
; 332.900 ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.384      ;
; 332.913 ; button_pulse_ps.DETECT                 ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.371      ;
; 332.925 ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.359      ;
; 332.925 ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.359      ;
; 332.925 ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.359      ;
; 332.934 ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.350      ;
; 332.934 ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 333.333      ; -0.036     ; 0.350      ;
+---------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                          ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack      ; From Node       ; To Node         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.171     ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; -0.171     ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.593      ;
; 0.072      ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.500        ; -0.110     ; 0.350      ;
; 0.351      ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.351      ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.571      ;
; 0.563      ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 1.000        ; -0.110     ; 0.359      ;
; 249998.985 ; count_2hz[1]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.965      ;
; 249998.989 ; count_2hz[1]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.961      ;
; 249998.995 ; count_2hz[0]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.955      ;
; 249999.032 ; count_2hz[0]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.918      ;
; 249999.047 ; count_2hz[3]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.903      ;
; 249999.051 ; count_2hz[3]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.899      ;
; 249999.053 ; count_2hz[1]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.897      ;
; 249999.057 ; count_2hz[1]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.893      ;
; 249999.063 ; count_2hz[2]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.887      ;
; 249999.063 ; count_2hz[0]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.887      ;
; 249999.099 ; count_2hz[2]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.851      ;
; 249999.100 ; count_2hz[0]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.850      ;
; 249999.115 ; count_2hz[3]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.835      ;
; 249999.116 ; count_2hz[5]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.834      ;
; 249999.119 ; count_2hz[3]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.831      ;
; 249999.120 ; count_2hz[5]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.830      ;
; 249999.121 ; count_2hz[1]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.829      ;
; 249999.125 ; count_2hz[1]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.825      ;
; 249999.131 ; count_2hz[2]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.819      ;
; 249999.131 ; count_2hz[0]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.819      ;
; 249999.132 ; count_2hz[4]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.818      ;
; 249999.167 ; count_2hz[2]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.783      ;
; 249999.168 ; count_2hz[4]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.782      ;
; 249999.168 ; count_2hz[0]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.782      ;
; 249999.199 ; count_2hz[0]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.751      ;
; 249999.199 ; count_2hz[6]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.751      ;
; 249999.199 ; count_2hz[2]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.751      ;
; 249999.200 ; count_2hz[4]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.750      ;
; 249999.403 ; count_2hz[0]    ; count_2hz[0]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.547      ;
; 249999.403 ; count_2hz[2]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.547      ;
; 249999.404 ; count_2hz[6]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.546      ;
; 249999.404 ; count_2hz[4]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.546      ;
; 249999.412 ; count_2hz[3]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.538      ;
; 249999.413 ; count_2hz[5]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.537      ;
; 249999.417 ; count_2hz[1]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.533      ;
; 249999.428 ; debounce_cnt[0] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.522      ;
; 249999.566 ; debounce_cnt[0] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.384      ;
; 249999.566 ; count_2hz[7]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.384      ;
; 249999.578 ; debounce_cnt[1] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.372      ;
; 249999.591 ; debounce_cnt[0] ; debounce_cnt[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.359      ;
; 249999.591 ; debounce_cnt[1] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 250000.000   ; -0.037     ; 0.359      ;
+------------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'digit_clk'                                                                         ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node       ; To Node         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; 0.150 ; digit_seq_ps[2] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.801      ;
; 0.171 ; digit_seq_ps[2] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.780      ;
; 0.235 ; digit_seq_ps[0] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.716      ;
; 0.235 ; digit_seq_ps[0] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.716      ;
; 0.304 ; digit_seq_ps[1] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.647      ;
; 0.316 ; digit_seq_ps[1] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.635      ;
; 0.386 ; digit_seq_ps[2] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.565      ;
; 0.560 ; digit_seq_ps[1] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 1.000        ; -0.036     ; 0.391      ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                            ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack      ; From Node                ; To Node                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.249      ; q_stretch                ; q0_sync                  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 1.000        ; -0.323     ; 0.375      ;
; 104165.454 ; start_send_ps            ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.162      ;
; 104165.454 ; start_send_ps            ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.162      ;
; 104165.454 ; start_send_ps            ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.162      ;
; 104165.454 ; start_send_ps            ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.162      ;
; 104165.458 ; start_send_ps            ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.158      ;
; 104165.458 ; start_send_ps            ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.158      ;
; 104165.458 ; start_send_ps            ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.158      ;
; 104165.614 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.002      ;
; 104165.614 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.002      ;
; 104165.614 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.002      ;
; 104165.614 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 1.002      ;
; 104165.621 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.995      ;
; 104165.621 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.995      ;
; 104165.621 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.995      ;
; 104165.794 ; adc_data_rdy_stretch     ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.033     ; 0.826      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.927 ; start_send_ps            ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.689      ;
; 104165.982 ; serial_bit_cntr_ps.BIT_8 ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.634      ;
; 104166.006 ; adc_data_rdy_stretch     ; q0_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.036     ; 0.611      ;
; 104166.059 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.557      ;
; 104166.067 ; uart_main_ps.CHAR_5      ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.549      ;
; 104166.086 ; uart_main_ps.CHAR_1      ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.530      ;
; 104166.091 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.525      ;
; 104166.098 ; uart_main_ps.CHAR_0      ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.518      ;
; 104166.137 ; uart_main_ps.CHAR_6      ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.479      ;
; 104166.150 ; adc_data_rdy_stretch     ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.036     ; 0.467      ;
; 104166.152 ; uart_main_ps.CHAR_2      ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.464      ;
; 104166.153 ; uart_main_ps.CHAR_3      ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.463      ;
; 104166.159 ; uart_main_ps.CHAR_4      ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.457      ;
; 104166.164 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.452      ;
; 104166.169 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.447      ;
; 104166.172 ; q0_sync                  ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.036     ; 0.445      ;
; 104166.176 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.440      ;
; 104166.177 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.439      ;
; 104166.178 ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.438      ;
; 104166.209 ; uart_main_ps.CHAR_6      ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.407      ;
; 104166.232 ; serial_bit_cntr_ps.BIT_9 ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.384      ;
; 104166.242 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.374      ;
; 104166.243 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.373      ;
; 104166.245 ; q1_sync                  ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.036     ; 0.372      ;
; 104166.257 ; start_send_ps            ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.037     ; 0.359      ;
; 104166.258 ; adc_data_rdy_stretch     ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 104166.666   ; -0.036     ; 0.359      ;
+------------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                        ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack    ; From Node                                               ; To Node                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 6509.079 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.276      ;
; 6509.079 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.276      ;
; 6509.079 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.276      ;
; 6509.124 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.231      ;
; 6509.124 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.231      ;
; 6509.124 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.231      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.135 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.220      ;
; 6509.230 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.125      ;
; 6509.230 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.125      ;
; 6509.230 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.125      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.251 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.104      ;
; 6509.301 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.054      ;
; 6509.301 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.054      ;
; 6509.301 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 1.054      ;
; 6509.329 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 1.037      ;
; 6509.408 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.959      ;
; 6509.408 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.959      ;
; 6509.410 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.957      ;
; 6509.450 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.917      ;
; 6509.455 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.912      ;
; 6509.464 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.902      ;
; 6509.468 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.899      ;
; 6509.473 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.894      ;
; 6509.491 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.876      ;
; 6509.502 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.865      ;
; 6509.510 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.857      ;
; 6509.524 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.843      ;
; 6509.524 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.843      ;
; 6509.549 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.818      ;
; 6509.561 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.806      ;
; 6509.580 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.787      ;
; 6509.589 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.778      ;
; 6509.602 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.764      ;
; 6509.604 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.763      ;
; 6509.608 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.758      ;
; 6509.616 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.751      ;
; 6509.626 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.741      ;
; 6509.632 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.735      ;
; 6509.650 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.717      ;
; 6509.657 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.710      ;
; 6509.668 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.699      ;
; 6509.671 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.696      ;
; 6509.688 ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.048     ; 0.667      ;
; 6509.731 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.636      ;
; 6509.760 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.607      ;
; 6509.766 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.601      ;
; 6509.792 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.575      ;
; 6509.802 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.565      ;
; 6509.805 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.562      ;
; 6509.807 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.560      ;
; 6509.812 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.555      ;
; 6509.835 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.531      ;
; 6509.903 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.464      ;
; 6509.915 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.452      ;
; 6509.919 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.447      ;
; 6509.921 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.445      ;
; 6509.922 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.444      ;
; 6509.922 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.444      ;
; 6509.926 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.440      ;
; 6509.927 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.439      ;
; 6509.929 ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.437      ;
; 6509.929 ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.437      ;
; 6509.929 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.437      ;
; 6509.948 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.419      ;
; 6509.977 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.390      ;
; 6509.978 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.389      ;
; 6509.983 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.384      ;
; 6509.986 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.381      ;
; 6509.990 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.376      ;
; 6509.991 ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.375      ;
; 6509.991 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.375      ;
; 6509.992 ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.374      ;
; 6509.993 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.373      ;
; 6509.993 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.373      ;
; 6509.993 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.373      ;
; 6509.994 ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.372      ;
; 6509.994 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.372      ;
; 6509.994 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.372      ;
; 6509.994 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.037     ; 0.372      ;
; 6510.008 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.359      ;
; 6510.008 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.359      ;
; 6510.008 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.359      ;
; 6510.017 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.350      ;
; 6510.017 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.350      ;
; 6510.017 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.350      ;
; 6510.017 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.350      ;
; 6510.017 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6510.416     ; -0.036     ; 0.350      ;
+----------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                       ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node       ; To Node         ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.116 ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.307      ;
; 0.186  ; debounce_cnt[1] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.189  ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.189  ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.134      ; 0.612      ;
; 0.192  ; debounce_cnt[1] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.313      ;
; 0.193  ; debounce_cnt[0] ; debounce_cnt[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.314      ;
; 0.201  ; debounce_cnt[0] ; debounce_cnt[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.322      ;
; 0.204  ; count_2hz[7]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.325      ;
; 0.297  ; count_2hz[1]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298  ; count_2hz[6]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.419      ;
; 0.298  ; count_2hz[3]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.419      ;
; 0.299  ; count_2hz[5]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; count_2hz[4]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; count_2hz[2]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.420      ;
; 0.301  ; debounce_cnt[0] ; digit_clk       ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.422      ;
; 0.307  ; count_2hz[0]    ; count_2hz[0]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.428      ;
; 0.391  ; digit_clk       ; digit_clk       ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.314      ;
; 0.446  ; count_2hz[1]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.567      ;
; 0.447  ; count_2hz[3]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.568      ;
; 0.448  ; count_2hz[5]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.569      ;
; 0.456  ; count_2hz[6]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456  ; count_2hz[0]    ; count_2hz[1]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.577      ;
; 0.457  ; count_2hz[2]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.578      ;
; 0.457  ; count_2hz[4]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.578      ;
; 0.459  ; count_2hz[0]    ; count_2hz[2]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.580      ;
; 0.460  ; count_2hz[2]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.581      ;
; 0.460  ; count_2hz[4]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.581      ;
; 0.509  ; count_2hz[1]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.630      ;
; 0.510  ; count_2hz[3]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.631      ;
; 0.511  ; count_2hz[5]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.632      ;
; 0.512  ; count_2hz[1]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.633      ;
; 0.513  ; count_2hz[3]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.634      ;
; 0.522  ; count_2hz[0]    ; count_2hz[3]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.643      ;
; 0.523  ; count_2hz[2]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.644      ;
; 0.523  ; count_2hz[4]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.644      ;
; 0.525  ; count_2hz[0]    ; count_2hz[4]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.646      ;
; 0.526  ; count_2hz[2]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.647      ;
; 0.575  ; count_2hz[1]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.696      ;
; 0.576  ; count_2hz[3]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.697      ;
; 0.578  ; count_2hz[1]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.699      ;
; 0.588  ; count_2hz[0]    ; count_2hz[5]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.709      ;
; 0.589  ; count_2hz[2]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.710      ;
; 0.591  ; count_2hz[0]    ; count_2hz[6]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.712      ;
; 0.641  ; count_2hz[1]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.762      ;
; 0.654  ; count_2hz[0]    ; count_2hz[7]    ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.775      ;
; 0.708  ; digit_clk       ; count_2hz[7]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[5]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[6]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[4]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[3]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[2]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[0]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
; 0.708  ; digit_clk       ; count_2hz[1]    ; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.500       ; 0.134      ; 0.631      ;
+--------+-----------------+-----------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                     ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                              ; To Node                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.106 ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.307      ;
; -0.099 ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.314      ;
; 0.187  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.200  ; button_pulse_ps.DETECT                 ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.320      ;
; 0.200  ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.IDLE  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.320      ;
; 0.204  ; button_pulse_ps.PULSE                  ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
; 0.205  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.618      ;
; 0.214  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.617      ;
; 0.216  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.336      ;
; 0.247  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.660      ;
; 0.259  ; two_hz_sync                            ; button_pulse_ps.DETECT                 ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.379      ;
; 0.273  ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.676      ;
; 0.281  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.401      ;
; 0.284  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.404      ;
; 0.284  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.404      ;
; 0.297  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.STOP  ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.710      ;
; 0.309  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.429      ;
; 0.312  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.313  ; button_pulse_ps.PULSE                  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.433      ;
; 0.315  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.435      ;
; 0.320  ; two_hz_sync                            ; button_pulse_ps.PULSE                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.440      ;
; 0.331  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.744      ;
; 0.368  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.781      ;
; 0.368  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.781      ;
; 0.368  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.781      ;
; 0.368  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.781      ;
; 0.385  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.505      ;
; 0.388  ; adc_control:adc_control_0|adc_ps.IDLE  ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.508      ;
; 0.413  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.826      ;
; 0.413  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.826      ;
; 0.413  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.826      ;
; 0.413  ; adc_control:adc_control_0|s_clk        ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.124      ; 0.826      ;
; 0.442  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.448  ; q0_2hz_sync                            ; two_hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.502  ; adc_control:adc_control_0|bit_count[3] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.622      ;
; 0.509  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.552  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.672      ;
; 0.570  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.690      ;
; 0.769  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[3] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.889      ;
; 0.769  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.889      ;
; 0.769  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.889      ;
; 0.769  ; adc_control:adc_control_0|adc_ps.START ; adc_control:adc_control_0|bit_count[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.889      ;
; 0.777  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|bit_count[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.897      ;
; 0.949  ; adc_control:adc_control_0|bit_count[1] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 1.069      ;
; 0.967  ; adc_control:adc_control_0|bit_count[0] ; adc_control:adc_control_0|adc_ps.START ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 1.087      ;
; 1.112  ; adc_control:adc_control_0|bit_count[2] ; adc_control:adc_control_0|adc_ps.STOP  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 1.232      ;
; 1.684  ; count_2hz[1]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.621      ;
; 1.743  ; count_2hz[2]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.680      ;
; 1.785  ; count_2hz[3]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.722      ;
; 1.786  ; count_2hz[0]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.723      ;
; 1.831  ; count_2hz[4]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.768      ;
; 1.891  ; count_2hz[6]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.828      ;
; 1.933  ; count_2hz[5]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.870      ;
; 2.007  ; count_2hz[7]                           ; q0_2hz_sync                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.250       ; 0.083      ; 1.944      ;
+--------+----------------------------------------+----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.183 ; q_stretch                ; q0_sync                  ; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.041     ; 0.316      ;
; 0.186 ; start_send_ps            ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.193 ; serial_bit_cntr_ps.BIT_6 ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; serial_bit_cntr_ps.BIT_7 ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; adc_data_rdy_stretch     ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; q1_sync                  ; adc_data_rdy_stretch     ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.207 ; serial_bit_cntr_ps.BIT_9 ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.328      ;
; 0.226 ; uart_main_ps.CHAR_6      ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.347      ;
; 0.253 ; q0_sync                  ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.266 ; serial_bit_cntr_ps.BIT_0 ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.387      ;
; 0.267 ; serial_bit_cntr_ps.BIT_2 ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.388      ;
; 0.267 ; serial_bit_cntr_ps.BIT_4 ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.388      ;
; 0.272 ; serial_bit_cntr_ps.BIT_5 ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.393      ;
; 0.276 ; adc_data_rdy_stretch     ; q1_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.396      ;
; 0.279 ; serial_bit_cntr_ps.BIT_3 ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.400      ;
; 0.281 ; uart_main_ps.CHAR_4      ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.402      ;
; 0.283 ; uart_main_ps.CHAR_6      ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.404      ;
; 0.286 ; uart_main_ps.CHAR_3      ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.407      ;
; 0.286 ; uart_main_ps.CHAR_2      ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.407      ;
; 0.336 ; uart_main_ps.CHAR_0      ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.457      ;
; 0.338 ; serial_bit_cntr_ps.BIT_8 ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.459      ;
; 0.346 ; uart_main_ps.CHAR_1      ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.467      ;
; 0.348 ; uart_main_ps.CHAR_5      ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.469      ;
; 0.363 ; serial_bit_cntr_ps.BIT_1 ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.484      ;
; 0.387 ; adc_data_rdy_stretch     ; q0_sync                  ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.507      ;
; 0.413 ; serial_bit_cntr_ps.BIT_8 ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.534      ;
; 0.533 ; adc_data_rdy_stretch     ; start_send_ps            ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.040      ; 0.657      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_0 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_1 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_2 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_3 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_4 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_5 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_6 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_7 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_8 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.565 ; start_send_ps            ; serial_bit_cntr_ps.BIT_9 ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.686      ;
; 0.884 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.005      ;
; 0.884 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.005      ;
; 0.884 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.005      ;
; 0.887 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.008      ;
; 0.887 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.008      ;
; 0.887 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.008      ;
; 0.887 ; serial_bit_cntr_ps.BIT_9 ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.008      ;
; 0.972 ; start_send_ps            ; uart_main_ps.CHAR_1      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.093      ;
; 0.972 ; start_send_ps            ; uart_main_ps.CHAR_6      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.093      ;
; 0.972 ; start_send_ps            ; uart_main_ps.CHAR_0      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.093      ;
; 0.979 ; start_send_ps            ; uart_main_ps.CHAR_2      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.100      ;
; 0.979 ; start_send_ps            ; uart_main_ps.CHAR_5      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.100      ;
; 0.979 ; start_send_ps            ; uart_main_ps.CHAR_4      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.100      ;
; 0.979 ; start_send_ps            ; uart_main_ps.CHAR_3      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 1.100      ;
+-------+--------------------------+--------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                      ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                               ; To Node                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_13              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_7               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.314      ;
; 0.194 ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.316      ;
; 0.195 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.316      ;
; 0.196 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_12              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.317      ;
; 0.200 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.320      ;
; 0.205 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.325      ;
; 0.206 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.326      ;
; 0.208 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.328      ;
; 0.227 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.347      ;
; 0.253 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.373      ;
; 0.266 ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.387      ;
; 0.266 ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.387      ;
; 0.266 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_1               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_2               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.387      ;
; 0.267 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_5               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_6               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.388      ;
; 0.267 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_3               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_4               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.388      ;
; 0.268 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.388      ;
; 0.270 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.391      ;
; 0.270 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.391      ;
; 0.271 ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.392      ;
; 0.272 ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.393      ;
; 0.276 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.396      ;
; 0.279 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.399      ;
; 0.311 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.431      ;
; 0.326 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.446      ;
; 0.335 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.455      ;
; 0.342 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.462      ;
; 0.346 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_10              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_11              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.466      ;
; 0.371 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.491      ;
; 0.375 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.495      ;
; 0.377 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[1]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.497      ;
; 0.427 ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 0.556      ;
; 0.429 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.549      ;
; 0.462 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_8               ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.583      ;
; 0.467 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.587      ;
; 0.469 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.589      ;
; 0.471 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.591      ;
; 0.472 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.592      ;
; 0.491 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_14              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.612      ;
; 0.491 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.611      ;
; 0.525 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.645      ;
; 0.532 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.652      ;
; 0.545 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.665      ;
; 0.546 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.666      ;
; 0.563 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.683      ;
; 0.569 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.689      ;
; 0.581 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[2]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.701      ;
; 0.591 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.711      ;
; 0.593 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.713      ;
; 0.598 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.718      ;
; 0.606 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.NOT_DETECT      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.726      ;
; 0.608 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_9               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.728      ;
; 0.642 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.STOP_BIT        ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.762      ;
; 0.692 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.812      ;
; 0.692 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.812      ;
; 0.737 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.EDGE_DETECTED   ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.857      ;
; 0.758 ; uart_rcv:uart_rcv_0|sync_data                           ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_0               ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.878      ;
; 0.782 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|data_bit[0]                         ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.902      ;
; 0.782 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[7]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.902      ;
; 0.877 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.006      ;
; 0.877 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.006      ;
; 0.877 ; uart_rcv:uart_rcv_0|data_bit[1]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.006      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.907 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.036      ;
; 0.935 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.064      ;
; 0.935 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.064      ;
; 0.935 ; uart_rcv:uart_rcv_0|data_bit[2]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.064      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[6]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[1]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[2]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[3]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[4]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[5]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 0.997 ; uart_rcv:uart_rcv_0|rx_state_tracker_ps.START_VALIDATED ; uart_rcv:uart_rcv_0|rx_shift_reg[0]                     ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.126      ;
; 1.007 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.136      ;
; 1.007 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.136      ;
; 1.007 ; uart_rcv:uart_rcv_0|bit_16x_cntr_ps.BIT_15              ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.136      ;
; 1.052 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[1]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.181      ;
; 1.052 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[0]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.181      ;
; 1.052 ; uart_rcv:uart_rcv_0|data_bit[0]                         ; uart_rcv:uart_rcv_0|uart_rx_output[2]                   ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.045      ; 1.181      ;
+-------+---------------------------------------------------------+---------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'digit_clk'                                                                          ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node       ; To Node         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+
; 0.216 ; digit_seq_ps[1] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.336      ;
; 0.348 ; digit_seq_ps[2] ; digit_seq_ps[0] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.468      ;
; 0.452 ; digit_seq_ps[1] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.572      ;
; 0.472 ; digit_seq_ps[1] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.592      ;
; 0.508 ; digit_seq_ps[0] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.628      ;
; 0.508 ; digit_seq_ps[0] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.628      ;
; 0.579 ; digit_seq_ps[2] ; digit_seq_ps[2] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.699      ;
; 0.603 ; digit_seq_ps[2] ; digit_seq_ps[1] ; digit_clk    ; digit_clk   ; 0.000        ; 0.036      ; 0.723      ;
+-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'adc_control:adc_control_0|s_clk'                                                                                                                                                 ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; Slack ; From Node                              ; To Node             ; Launch Clock                                               ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+
; 0.217 ; adc_sr_data_out[10]                    ; adc_sr_data_out[11] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.337      ;
; 0.278 ; adc_sr_data_out[6]                     ; adc_sr_data_out[7]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.398      ;
; 0.280 ; adc_sr_data_out[9]                     ; adc_sr_data_out[10] ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.400      ;
; 0.280 ; adc_sr_data_out[7]                     ; adc_sr_data_out[8]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.400      ;
; 0.282 ; adc_sr_data_out[1]                     ; adc_sr_data_out[2]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.402      ;
; 0.292 ; adc_sr_data_out[5]                     ; adc_sr_data_out[6]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; adc_sr_data_out[0]                     ; adc_sr_data_out[1]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.413      ;
; 0.347 ; adc_sr_data_out[3]                     ; adc_sr_data_out[4]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.467      ;
; 0.350 ; adc_sr_data_out[8]                     ; adc_sr_data_out[9]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.470      ;
; 0.358 ; adc_sr_data_out[4]                     ; adc_sr_data_out[5]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.478      ;
; 0.360 ; adc_sr_data_out[2]                     ; adc_sr_data_out[3]  ; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk ; 0.000        ; 0.036      ; 0.480      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.427 ; adc_control:adc_control_0|bit_count[3] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.441      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[4]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[3]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[2]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[1]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[0]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[5]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[6]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[7]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[8]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[9]  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[10] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
; 0.441 ; adc_control:adc_control_0|bit_count[2] ; adc_sr_data_out[11] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk ; 0.000        ; 1.850      ; 2.455      ;
+-------+----------------------------------------+---------------------+------------------------------------------------------------+---------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'adc_control:adc_control_0|adc_ps.STOP'                                                                                                                  ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node   ; Launch Clock                                               ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; -0.066 ; adc_data_rdy_stretch ; q_stretch ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 1.000        ; 0.041      ; 1.024      ;
+--------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'adc_control:adc_control_0|adc_ps.STOP'                                                                                                                  ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node   ; Launch Clock                                               ; Latch Clock                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+
; 0.437 ; adc_data_rdy_stretch ; q_stretch ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 0.000        ; 0.323      ; 0.904      ;
+-------+----------------------+-----------+------------------------------------------------------------+---------------------------------------+--------------+------------+------------+


----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 665.371 ns




+----------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                        ;
+-------------------------------------------------------------+----------+--------+----------+---------+---------------------+
; Clock                                                       ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------------+----------+--------+----------+---------+---------------------+
; Worst-case Slack                                            ; -2.232   ; -0.265 ; -0.832   ; 0.437   ; -1.000              ;
;  adc_control:adc_control_0|adc_ps.STOP                      ; N/A      ; N/A    ; -0.832   ; 0.437   ; -1.000              ;
;  adc_control:adc_control_0|s_clk                            ; -2.232   ; 0.217  ; N/A      ; N/A     ; -1.000              ;
;  digit_clk                                                  ; -0.539   ; 0.216  ; N/A      ; N/A     ; -1.000              ;
;  inclk0_sig                                                 ; N/A      ; N/A    ; N/A      ; N/A     ; 9.587               ;
;  lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -1.406   ; -0.259 ; N/A      ; N/A     ; 166.412             ;
;  lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.530   ; -0.265 ; N/A      ; N/A     ; 124999.743          ;
;  lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 6508.094 ; 0.187  ; N/A      ; N/A     ; 3254.951            ;
;  lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.264   ; 0.183  ; N/A      ; N/A     ; 52083.081           ;
; Design-wide TNS                                             ; -42.632  ; -0.524 ; -0.832   ; 0.0     ; -16.0               ;
;  adc_control:adc_control_0|adc_ps.STOP                      ; N/A      ; N/A    ; -0.832   ; 0.000   ; -1.000              ;
;  adc_control:adc_control_0|s_clk                            ; -26.784  ; 0.000  ; N/A      ; N/A     ; -12.000             ;
;  digit_clk                                                  ; -1.129   ; 0.000  ; N/A      ; N/A     ; -3.000              ;
;  inclk0_sig                                                 ; N/A      ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; -10.138  ; -0.259 ; N/A      ; N/A     ; 0.000               ;
;  lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; -4.317   ; -0.265 ; N/A      ; N/A     ; 0.000               ;
;  lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000    ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; -0.264   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
+-------------------------------------------------------------+----------+--------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                 ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; segment_data[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; segment_data[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sel0                ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sel1                ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sel2                ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; enable3to8          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; enable3to8_n        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; pwm_output          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; adc_cs_n            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; s_clk               ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; adc_serial_data_out ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; pc_serial_data_out  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; reset_n                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; adc_serial_data_in      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; inclk0_sig              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; pc_serial_data_in       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; segment_data[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; segment_data[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; sel0                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; sel1                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; sel2                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; enable3to8          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; enable3to8_n        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; pwm_output          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; adc_cs_n            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; s_clk               ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; adc_serial_data_out ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.95e-09 V                   ; 2.38 V              ; -0.016 V            ; 0.22 V                               ; 0.025 V                              ; 3.06e-10 s                  ; 3.3e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.95e-09 V                  ; 2.38 V             ; -0.016 V           ; 0.22 V                              ; 0.025 V                             ; 3.06e-10 s                 ; 3.3e-10 s                  ; Yes                       ; Yes                       ;
; pc_serial_data_out  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.44e-09 V                   ; 2.39 V              ; -0.0265 V           ; 0.2 V                                ; 0.033 V                              ; 2.94e-10 s                  ; 3.12e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.44e-09 V                  ; 2.39 V             ; -0.0265 V          ; 0.2 V                               ; 0.033 V                             ; 2.94e-10 s                 ; 3.12e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 3.45e-09 V                   ; 2.38 V              ; -0.0609 V           ; 0.148 V                              ; 0.095 V                              ; 2.82e-10 s                  ; 2.59e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 3.45e-09 V                  ; 2.38 V             ; -0.0609 V          ; 0.148 V                             ; 0.095 V                             ; 2.82e-10 s                 ; 2.59e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.61e-09 V                   ; 2.38 V              ; -0.00274 V          ; 0.141 V                              ; 0.006 V                              ; 4.7e-10 s                   ; 6.02e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.61e-09 V                  ; 2.38 V             ; -0.00274 V         ; 0.141 V                             ; 0.006 V                             ; 4.7e-10 s                  ; 6.02e-10 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; segment_data[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; sel0                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; sel1                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; sel2                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; enable3to8          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; enable3to8_n        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; pwm_output          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; adc_cs_n            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; s_clk               ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; adc_serial_data_out ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.06e-06 V                   ; 2.36 V              ; -0.00724 V          ; 0.107 V                              ; 0.02 V                               ; 4.5e-10 s                   ; 4.25e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.06e-06 V                  ; 2.36 V             ; -0.00724 V         ; 0.107 V                             ; 0.02 V                              ; 4.5e-10 s                  ; 4.25e-10 s                 ; Yes                       ; Yes                       ;
; pc_serial_data_out  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.16e-07 V                   ; 2.36 V              ; -0.00476 V          ; 0.096 V                              ; 0.013 V                              ; 4.39e-10 s                  ; 4.15e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.16e-07 V                  ; 2.36 V             ; -0.00476 V         ; 0.096 V                             ; 0.013 V                             ; 4.39e-10 s                 ; 4.15e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.74e-07 V                   ; 2.36 V              ; -0.0201 V           ; 0.072 V                              ; 0.033 V                              ; 4.04e-10 s                  ; 3.29e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.74e-07 V                  ; 2.36 V             ; -0.0201 V          ; 0.072 V                             ; 0.033 V                             ; 4.04e-10 s                 ; 3.29e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.45e-07 V                   ; 2.35 V              ; -0.00643 V          ; 0.081 V                              ; 0.031 V                              ; 5.31e-10 s                  ; 7.59e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.45e-07 V                  ; 2.35 V             ; -0.00643 V         ; 0.081 V                             ; 0.031 V                             ; 5.31e-10 s                 ; 7.59e-10 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; segment_data[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; segment_data[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sel0                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sel1                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sel2                ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; enable3to8          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; enable3to8_n        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; pwm_output          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; adc_cs_n            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; s_clk               ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; adc_serial_data_out ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.05e-08 V                   ; 2.72 V              ; -0.0349 V           ; 0.173 V                              ; 0.1 V                                ; 2.72e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.05e-08 V                  ; 2.72 V             ; -0.0349 V          ; 0.173 V                             ; 0.1 V                               ; 2.72e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; pc_serial_data_out  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.74e-08 V                   ; 2.73 V              ; -0.0384 V           ; 0.169 V                              ; 0.089 V                              ; 2.7e-10 s                   ; 2.62e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.74e-08 V                  ; 2.73 V             ; -0.0384 V          ; 0.169 V                             ; 0.089 V                             ; 2.7e-10 s                  ; 2.62e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.74 V              ; -0.06 V             ; 0.158 V                              ; 0.08 V                               ; 2.68e-10 s                  ; 2.19e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.74 V             ; -0.06 V            ; 0.158 V                             ; 0.08 V                              ; 2.68e-10 s                 ; 2.19e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.54e-08 V                   ; 2.7 V               ; -0.00943 V          ; 0.276 V                              ; 0.035 V                              ; 3.19e-10 s                  ; 4.99e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.54e-08 V                  ; 2.7 V              ; -0.00943 V         ; 0.276 V                             ; 0.035 V                             ; 3.19e-10 s                 ; 4.99e-10 s                 ; No                        ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                     ;
+------------------------------------------------------------+------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+----------+----------+----------+----------+
; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk                            ; 11       ; 0        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk                            ; 24       ; 0        ; 0        ; 0        ;
; digit_clk                                                  ; digit_clk                                                  ; 8        ; 0        ; 0        ; 0        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 1        ; 0        ; 0        ;
; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 7        ; 7        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 34       ; 0        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 8        ; 0        ; 0        ; 0        ;
; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 9        ; 9        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 41       ; 0        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 102      ; 0        ; 0        ; 0        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 0        ; 0        ; 0        ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 50       ; 0        ; 0        ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                      ;
+------------------------------------------------------------+------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+----------+----------+----------+----------+
; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk                            ; 11       ; 0        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|s_clk                            ; 24       ; 0        ; 0        ; 0        ;
; digit_clk                                                  ; digit_clk                                                  ; 8        ; 0        ; 0        ; 0        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 1        ; 0        ; 0        ;
; adc_control:adc_control_0|s_clk                            ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 7        ; 7        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 34       ; 0        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; 8        ; 0        ; 0        ; 0        ;
; digit_clk                                                  ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 9        ; 9        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; 41       ; 0        ; 0        ; 0        ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; 102      ; 0        ; 0        ; 0        ;
; adc_control:adc_control_0|adc_ps.STOP                      ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 0        ; 0        ; 0        ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; 50       ; 0        ; 0        ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                             ;
+------------------------------------------------------------+---------------------------------------+----------+----------+----------+----------+
; From Clock                                                 ; To Clock                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------------+---------------------------------------+----------+----------+----------+----------+
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 1        ; 0        ; 0        ; 0        ;
+------------------------------------------------------------+---------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                              ;
+------------------------------------------------------------+---------------------------------------+----------+----------+----------+----------+
; From Clock                                                 ; To Clock                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------------------------+---------------------------------------+----------+----------+----------+----------+
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; adc_control:adc_control_0|adc_ps.STOP ; 1        ; 0        ; 0        ; 0        ;
+------------------------------------------------------------+---------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths Summary                    ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 3     ; 3    ;
; Unconstrained Input Port Paths  ; 97    ; 97   ;
; Unconstrained Output Ports      ; 15    ; 15   ;
; Unconstrained Output Port Paths ; 157   ; 157  ;
+---------------------------------+-------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Status Summary                                                                                                                              ;
+------------------------------------------------------------+------------------------------------------------------------+-----------+-------------+
; Target                                                     ; Clock                                                      ; Type      ; Status      ;
+------------------------------------------------------------+------------------------------------------------------------+-----------+-------------+
; adc_control:adc_control_0|adc_ps.STOP                      ; adc_control:adc_control_0|adc_ps.STOP                      ; Base      ; Constrained ;
; adc_control:adc_control_0|s_clk                            ; adc_control:adc_control_0|s_clk                            ; Base      ; Constrained ;
; digit_clk                                                  ; digit_clk                                                  ; Base      ; Constrained ;
; inclk0_sig                                                 ; inclk0_sig                                                 ; Base      ; Constrained ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; Constrained ;
; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] ; Generated ; Constrained ;
; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ;
+------------------------------------------------------------+------------------------------------------------------------+-----------+-------------+


+-----------------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                                 ;
+--------------------+--------------------------------------------------------------------------------------+
; Input Port         ; Comment                                                                              ;
+--------------------+--------------------------------------------------------------------------------------+
; adc_serial_data_in ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pc_serial_data_in  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; reset_n            ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------------+--------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                                  ;
+---------------------+---------------------------------------------------------------------------------------+
; Output Port         ; Comment                                                                               ;
+---------------------+---------------------------------------------------------------------------------------+
; adc_cs_n            ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; adc_serial_data_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; enable3to8          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pc_serial_data_out  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; s_clk               ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sel0                ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sel1                ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sel2                ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+---------------------+---------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                                 ;
+--------------------+--------------------------------------------------------------------------------------+
; Input Port         ; Comment                                                                              ;
+--------------------+--------------------------------------------------------------------------------------+
; adc_serial_data_in ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pc_serial_data_in  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; reset_n            ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------------+--------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                                  ;
+---------------------+---------------------------------------------------------------------------------------+
; Output Port         ; Comment                                                                               ;
+---------------------+---------------------------------------------------------------------------------------+
; adc_cs_n            ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; adc_serial_data_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; enable3to8          ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pc_serial_data_out  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; s_clk               ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; segment_data[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sel0                ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sel1                ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sel2                ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+---------------------+---------------------------------------------------------------------------------------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
Info: Command: quartus_sta --no_banner lab6
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'lab6.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
    Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name inclk0_sig inclk0_sig
    Info (332110): create_generated_clock -source {lab6_pll1_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 50 -multiply_by 3 -duty_cycle 50.00 -name {lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]} {lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {lab6_pll1_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 12500 -duty_cycle 50.00 -name {lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]} {lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {lab6_pll1_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 15625 -multiply_by 48 -duty_cycle 50.00 -name {lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]} {lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {lab6_pll2_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 15625 -multiply_by 3 -duty_cycle 50.00 -name {lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]} {lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0]}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name adc_control:adc_control_0|s_clk adc_control:adc_control_0|s_clk
    Info (332105): create_clock -period 1.000 -name digit_clk digit_clk
    Info (332105): create_clock -period 1.000 -name adc_control:adc_control_0|adc_ps.STOP adc_control:adc_control_0|adc_ps.STOP
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -2.232
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.232             -26.784 adc_control:adc_control_0|s_clk 
    Info (332119):    -1.406             -10.138 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.539              -1.129 digit_clk 
    Info (332119):    -0.530              -4.317 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.264              -0.264 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):  6508.094               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case hold slack is -0.207
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.207              -0.207 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.195              -0.195 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.358               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.358               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.404               0.000 digit_clk 
    Info (332119):     0.414               0.000 adc_control:adc_control_0|s_clk 
Info (332146): Worst-case recovery slack is -0.832
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.832              -0.832 adc_control:adc_control_0|adc_ps.STOP 
Info (332146): Worst-case removal slack is 0.925
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.925               0.000 adc_control:adc_control_0|adc_ps.STOP 
Info (332146): Worst-case minimum pulse width slack is -1.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.000             -12.000 adc_control:adc_control_0|s_clk 
    Info (332119):    -1.000              -3.000 digit_clk 
    Info (332119):    -1.000              -1.000 adc_control:adc_control_0|adc_ps.STOP 
    Info (332119):     9.835               0.000 inclk0_sig 
    Info (332119):   166.415               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):  3254.955               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119): 52083.085               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 124999.747               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
Info (332114): Report Metastability: Found 1 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 1
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 664.338 ns
    Info (332114): 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -2.066
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.066             -24.792 adc_control:adc_control_0|s_clk 
    Info (332119):    -1.208              -8.590 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.382              -0.730 digit_clk 
    Info (332119):    -0.371              -2.968 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.086              -0.086 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):  6508.337               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case hold slack is -0.265
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.265              -0.265 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.259              -0.259 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.312               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.313               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.359               0.000 digit_clk 
    Info (332119):     0.375               0.000 adc_control:adc_control_0|s_clk 
Info (332146): Worst-case recovery slack is -0.685
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.685              -0.685 adc_control:adc_control_0|adc_ps.STOP 
Info (332146): Worst-case removal slack is 0.888
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.888               0.000 adc_control:adc_control_0|adc_ps.STOP 
Info (332146): Worst-case minimum pulse width slack is -1.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.000             -12.000 adc_control:adc_control_0|s_clk 
    Info (332119):    -1.000              -3.000 digit_clk 
    Info (332119):    -1.000              -1.000 adc_control:adc_control_0|adc_ps.STOP 
    Info (332119):     9.817               0.000 inclk0_sig 
    Info (332119):   166.412               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):  3254.951               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119): 52083.081               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 124999.743               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
Info (332114): Report Metastability: Found 1 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 1
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 664.596 ns
    Info (332114): 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.341
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.341             -16.092 adc_control:adc_control_0|s_clk 
    Info (332119):    -0.882              -6.493 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.171              -1.368 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.150               0.000 digit_clk 
    Info (332119):     0.249               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):  6509.079               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case hold slack is -0.116
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.116              -0.116 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.106              -0.106 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.183               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.216               0.000 digit_clk 
    Info (332119):     0.217               0.000 adc_control:adc_control_0|s_clk 
Info (332146): Worst-case recovery slack is -0.066
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.066              -0.066 adc_control:adc_control_0|adc_ps.STOP 
Info (332146): Worst-case removal slack is 0.437
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.437               0.000 adc_control:adc_control_0|adc_ps.STOP 
Info (332146): Worst-case minimum pulse width slack is -1.000
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -1.000             -12.000 adc_control:adc_control_0|s_clk 
    Info (332119):    -1.000              -3.000 digit_clk 
    Info (332119):    -1.000              -1.000 adc_control:adc_control_0|adc_ps.STOP 
    Info (332119):     9.587               0.000 inclk0_sig 
    Info (332119):   166.448               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):  3254.990               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119): 52083.117               0.000 lab6_pll2_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 124999.782               0.000 lab6_pll1_inst|altpll_component|auto_generated|pll1|clk[1] 
Info (332114): Report Metastability: Found 1 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 1
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 665.371 ns
    Info (332114): 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 1051 megabytes
    Info: Processing ended: Sat Jun 18 03:46:03 2016
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


