Usage: vsim [options] [[.][()]]... -default_radix radix|radix_flag[,radix_flag...] Set default radix and radix flags. Specifying just a radix will clear all radix flags. Specifying just radix flags will set the flags but leave the default radix unchanged. -help Print this message -version Print the version of the simulator . Specifies a library and associated design unit; multiple library/design unit specifications can be made. If no library is specified, the work library is used. --------------------------- VHDL and Verilog options --------------------------- -assertcover Keep assertion counts for coverage statistics -assertdebug Keep data for debugging assertion failures -assertfile Alternative file for recording assert messages -msgfile Alternative file for recording non-assert messages -assume Simulate PSL and Verilog assume directives same as assert directives -autoexclusionsdisable=fsm|assertions|all|none Turns on/off automatic fsm or assertions code coverage exclusions -autoprofile[=] Automatically collect profile data without requiring the use of profile commands. Specifying a profile database name is optional -attemptedimmedcovers Exclude unattempted immediate covers to participate in coverage calculations -batch Batch mode -c Command line mode -capacity Enable fine grain capacity analysis -colormap new Specifies that the window should have a new private colormap instead of using the default colormap for the screen. -coverage Allows enabled coverage statistics to be kept -coverenhanced Enables functionality which may change the appearance or content of coverage metrics. A detailed list of these changes can be found by searching in the release notes for 'coverenhanced'. This option only takes meaningful effect in letter releases (e.g. 10.2b). It has no effect in initial major releases (e.g. 10.2). -covercountnone Disables the default behavior to increment the count of all matching rows in condition and expression coverage UDP tables. Has no effect on FEC coverage. -coverstore Specifies the path where coverage data will be dumped during exit of a simulation run. The -testname argument is required for this option to specify a testname for the current simulation run. -do "" Execute on startup; can be a macro filename -display Specifies the name of the display to use. Does not apply to Windows platforms. -displaymsgmode Controls transcripting of display system task messages. Messages will appear in transcript and/or MsgViewer (.wlf file) Valid modes - tran, wlf, both (Default: tran) +delayed_timing_checks Causes timing checks to be performed on the delayed versions of input ports +dumpports+direction Provide port direction info in VCD file for dumpports +dumpports+unique Provide unique Extended VCD identifier for each port +dumpports+no_strength_range Ignore strength range when resolving conflicts +dumpports+collapse Collapse dumpport vectors into single VCD ids +dumpports+nocollapse Don't collapse dumpport vectors into single VCD ids +dumpports+force_direction Ignore driver location. Use port direction for input and output ports -f Read command line arguments from -optionset Calls an option set in modelsim.ini. -g= Specify generic/parameter default Value for Name -g = Alternate way to specify generic/parameter default Value for Name -G= Override generic/parameter with specified Value -G = Alternate way to override generic/parameter with specified Value -geometry Specifies the size and location of the main window. Where is of the form: WxH+X+Y -gblso Open the specified shared object with global symbol visibility. -gui Open the GUI without loading a design -i Force interactive mode -ignoreinilibs Ignore the libraries specified with the 'LibrarySearchPath' variable in the vsim section of the ini file -immedassert Enable SystemVerilog and VHDL immediate assertions -installcolormap Cause the application to use its own color map -keeploaded Prevent the simulator from unloading/reloading shared libraries -keeploadedrestart Prevent the simulator from unloading/reloading shared libraries during restart -keepstdout Do not redirect stdout to transcript window -l Write simulation log to (Default: transcript) -learn Learn the names of objects externally accessed at runtime (by methods such as PLI, VPI, Signal Spy, or CLI). .ocf, .ocm and .acc files created -lib Load top-level design units from (Default: work) -lic_noqueue Do not wait in the license queue when a license is not available -lic_vhdl Immediately reserve a VHDL license -lic_vlog Immediately reserve a Verilog license -lic_no_viewer Disable checkout of viewer license and always use a simulation license to view -lic_viewsim View with a simulation license if a viewer license is not available -logfile Write simulation log to (Default: transcript) -memprof Collect memory allocation profile data for use with current simulation -memprof+call Unwinds the call stack and collects the call tree information. -memprof[+file=] Collect memory allocation profile data for use with current simulation and copy raw data to -memprof[+fileonly=] Collect memory allocation profile data in raw format to -modelsimini Specify path to the modelsim.ini file -mlopt Optimize mixed language nets -multisource_delay min|max|latest Controls annotation of SDF INTERCONNECT construct (Default: max) +multisource_int_delays Enable multisource interconnect delays for both Verilog and VHDL -msglimit [all,|none,][-|+][,[-|+]...] Limit the listed messages to display five times -msglimitcount -msglimit [all,|none,][-|+][,[-|+]...] Limit the reporting of listed messages to user defined count -msgmode Controls transcripting of elaboration/runtime messages. Messages will appear in transcript and/or MsgViewer (.wlf file) Valid modes - tran, wlf, both (Default: tran) -multicount Specifies the single-bit or multi-bit count modes for bins of different coverage types -mvchome Location of Questa Verification IP installation. Overrides 'MvcHome' modelsim.ini setting -name Specifies the application name used by the interpreter for send commands. +no_notifier Disable notifier toggling for timing constraint violations -noappendclose Do not physically close VHDL files when they are opened in append mode. -noassertcover Do not keep assertion counts for coverage statistics -noassertdebug Do not keep data for debugging assertion failures -noassume Do not simulate PSL and Verilog assume directives -nocapacity Do not display capacity related information -noexcludehiz Do not automatically exclude rows with Hi-Z for expression coverage -noexcludeternary Disables the automatic exclusion of UCDB coverage data rows resulting from ternary expressions for the entire design. -nolog Do not generate a simulation log file -nopsl Disable PSL assertions -nostdout Do not write transcript to stdout (batch mode only) +no_tchk_msg Disable timing constraint error messages -note [,...] Change the severity of the listed messages to Note +notimingchecks Disable Verilog and VITAL timing checks -novhdlvariablelogging Disables higher performance VHDL variable logging -nosyncio Disables synchronization of I/O from different sources like C/C++ application(PLI,VPI,DPI) and GUI. vsim will perform better when it does not have to synchronize I/Os. This option is on by default with -batch -nowiremodelforce Restores the force command to previous usage (prior to version 10.0b) where an input port cannot be forced directly if it is mapped at a higher level in VHDL and mixed models. Signals must be forced at the top of the hierarchy connected to the input port. -onfinish Customize the kernel shutdown behavior at the end of simulation Valid modes - ask, stop, exit, final (Default: ask) -pa Enable PowerAware RTL mode -pa_allowtimezeroevent[=all] Enable corruption, isolation, or release of signals at time 0 for the following events: pa_corrupt_register, pa_iso_on and pa_iso_off. -pa_debugdir Specify the location for the writing and retrieval of post-simulation debug information for power aware simulations. -pa_disabletimezeroevent Disable the default behavior of the -pa_allowtimezeroevent switch. -pa_gls Enables gate-level simulation for Power Aware, performed on the top-of-design test bench (testbench_top). -pa_highlight Enables visual indication (highlighting) of power states of signals viewed in the Wave window. -pa_lib Use PA specific dumps from library. (Default: work) -pa_togglelimit= Instructs vsim to discontinue reporting an error (8906) for each signal that toggles during power off and issue note (8922) instead. The default value is 5. -pa_top Allow vsim to use different top level hierarchy for PA (Example: -pa_top /tb2/dut_inst -pa_zcorrupt Change the default corruption value used at power-down from 'X' to 'Z'. -debugdb[=] To create or use Schematic Debug database (Default: vsim.dbg) -postsimdataflow Needed with -debugdb, to enable post simulation dataflow -pedanticerrors Enforce strict language checks -permissive Relax some language error checks to warnings. -printsimstats[=[val][v]] Print simstats results Possible values: 0 - disable simstats, 1 - end of simulation(default) 2 - end of each run command and simulation, v - verbose stats -psl Enable PSL assertions -psloneattempt Force single PSL assertion coverage attempt -pslinfinitythreshold Redefine infinite clock tick for strong operators -quiet Do not report 'Loading...' messages -qwavedb=... Use qwavedb to log event data in place of wlf -runinit Execute run -init before command prompt or running -do files. -sdfmax[@] [=] Annotate VITAL or Verilog with maximum timing from , scaled by -sdfmaxerrors Max number of missing instances reported (default is 5) -sdfmin[@] [=] Annotate VITAL or Verilog with minimum timing from , scaled by -sdfminr[@] [=] Specifies when an instance of a Preoptimized Design Unit (vopt -pdu) with an associated default SDF file is to be re-annotated with minimum, typical, or maximum timing from the specified SDF file. -sdfnoerror Treat SDF errors as warnings -sdfnowarn Disable warnings from SDF annotator -sdfreport= Report unannotated/partially-annotated specify objects into +sdf_report_unannotated_insts Enable error messages for any un-annotated Verilog instances with specify blocks or VHDL instances with VITAL timing generics that are under regions of SDF annotation. -sdftyp[@] [=] Annotate VITAL or Verilog with typical timing from , scaled by +sdf_verbose Display SDF annotator status messages -showautoexcludprows Display auto-excluded UDP rows of table, in expression coverage -showlibsearchpath Show all the libraries which will be searched for precompiled modules -suppress [,...] Suppress the listed messages -stats[=[+-]] Enables simulation statistics are all,none,time,cmd,msg,perf,verbose,list,kb,eor -sync Executes all X server commands synchronously, so that errors are reported immediately. Does not apply to Windows platforms. -syncio Enable I/O synchronization with -batch option where I/O synchronization is disabled by default for optimal performance. -undefsyms=[] Generate stubs for undefined symbols in the shared libraries being loaded are on, off, verbose -t [1|10|100]fs|ps|ns|us|ms|sec Time resolution limit (VHDL default: resolution setting from .ini file) (Verilog default: minimum time_precision in the design) -tag Set tag for FLI/PLI tracing to -notoggleints Excludes VHDL integers from toggle coverage -testname Specifies a testname for the current simulation run. Required only when coverage data is saved in a coverstore. -togglemaxintvalues Sets max number of values saved for VHDL integers -togglemaxrealvalues Sets max number of values saved for SystemVerilog reals -togglemaxfixedsizearray Sets the limit on the size of Verilog unpacked fixed-size arrays that are included for toggle coverage -togglecountlimit Sets max count saved for a toggle node -togglewidthlimit Sets max width for vectors counted for toggles -togglevlogreal Includes Verilog real type in toggle coverage -togglefixedsizearray Includes Verilog unpacked fixed-size arrays, VHDL multi-d arrays and VHDL arrays-of-arrays in toggle coverage -togglevlogints Includes Verilog integers for toggle coverage -togglevhdlrecords Includes VHDL records for toggle coverage -notogglevlogints Excludes Verilog integers from toggle coverage -notogglevlogreal Excludes Verilog real type in toggle coverage -notogglefixedsizearray Excludes Verilog unpacked fixed-size arrays, VHDL multi-d arrays and VHDL arrays-of-arrays in toggle coverage -notogglevhdlrecords Excludes VHDL records from toggle coverage -nowlfdeleteonquit Preserve the current simulation WLF file (vsim.wlf) when the simulator exits. -togglepackedasvec Treat SystemVerilog packed structures and multi-d arrays as flattened vectors -togglevlogenumbits Treat SystemVerilog enums as reg-vectors for toggle coverage -extendedtogglemode [1|2|3] Change the level of support for extended toggles. The levels of support are: 1 - 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z') 2 - 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z' 3 - 0L->1H & 1H->0L & all 'Z' transitions -toggleportsonly Enable toggle statistics collection only for ports -toggledeglitch Enable toggle deglitching. Require signal stable longer than period value must be a time value with units -title Optional title for the Main window -trace_dpi Set DPI tracing to level . The default is 0 which turns off tracing. The levels of support are: 1 - turning on all tracing 0 - turning off all tracing (default) i - turning on the tracing of DPI import call only e - turning on the tracing of DPI export call only a - turning on the tracing of DPI import/export call arguments only -trace_foreign Set FLI/PLI tracing to level -ucdbteststatusmsgfilter Matching messages do not propagate their status to UCDB TESTSTATUS -unattemptedimmed Include immediate assertions to participate in assertion coverage calculations -valgrind "[options]" same as SystemC -valgrind option -vcdstim [=] Stimulate the top-level design or instances from an Extended VCD file -vhdlmergepdupackage VHDL packages with the same name and same library are shared between PDUs -vhdlseparatepdupackage VHDL packages with the same name and same library are not shared between PDUs -vhdlvariablelogging Enables higher performance VHDL variable logging -visual Specify the visual to use for the window. Does not apply to Windows platforms. -visualizer[=...] Visualizer interactive mode -view [=] View the contents of a WLF file -viewcov [=] View the contents of the coverage ucdb file -warning [,...] Change the severity of the listed messages to Warning -warning error Report all warnings as errors -wlf Specify the name of the WLF file (Default: vsim.wlf) -wlfcompress Create compressed WLF files. -wlflock Lock a WLF file. -wlfopt Turn on WLF file optimizations (default) -nowlfopt Turn off WLF file optimizations -nowlfcompress Turn off WLF file compression -nowlflock Turn off WLF file locking -wlfslim Specify maximum number of Megabytes to be saved in WLF file (Default: infinite) -wlftlim Specify maximum duration of time to be saved in WLF file (Default: all) -wlfcachesize Specify WLF reader cache size (per WLF file.) (Default: no reader cache) -wlfsimcachesize Specify WLF reader cache size for current simulation (Default: no reader cache) -wlfdeleteonquit Delete WLF file when simulation quits. -nowlfcollapse Log every item event and preserve event order. -wlfcollapsedelta Log item values only at end of iteration. (default) -wlfcollapsetime Log item values only at end of time step. --------------------------------- VHDL options --------------------------------- -absentisempty Treat non-existent VHDL files opened for read as empty -accessobjdebug Enable access value designated object debug features. -defaultstdlogicinittoz Sets the default VHDL initialization of std_logic to "Z" (high impedance) for ports of type OUT and INOUT. -nocollapse Disable optimization of internal port map connections -nofileshare Do not share file descriptors for VHDL files opened for write or append that have identical names -noglitch Disable VITAL glitch generation +no_glitch_msg Disable glitch error messages -oldvhdlforgennames Enable the use of a previous style of naming in VHDL for...generate statement iteration names in the design hierarchy. -stackcheck Enable runtime stack usage sanity checking. -std_input Use filename for VHDL textio STD_INPUT file -std_output Use filename for VHDL textio STD_OUTPUT file -strictvital Sacrifice performance for strict VITAL compliance -vital2.2b Select SDF mapping for VITAL 2.2b (Default: VITAL 95) -vital_fix_negative_setup_hold_sum Set negative time to zero when setuphold sum is negative -------------------------------- Verilog options ------------------------------- -allowcheckpointcpp 1|0 Turn on/off the support for checkpointing foreign C++ libraries. Must be used in the vsim session where a checkpoint is created. +alt_path_delays Use current output value instead of pending value when selecting inertial specify path output delay +bitblast[=[iopath|tcheck]] Bit-blast Verilog specify paths and/or tchecks with wide ports. Without the optional qualifiers operates on specify paths and tchecks. +bitblast=iopath bit-blasts specify paths with wide ports. +bitblast=tcheck bit-blasts tchecks with wide ports. -checkvifacedrivers 1|0 Include assignments through virtual interfaces in the multiple-driver analysis. -classdebug Enable class debug features. -nocvgcollapseembeddedinstances Turning off the optimization of collapsing embedded covergroup instances when type_option.merge_instances is set to zero. -cvgmaxrptrhscross Set the maximum cross bin BINRHS terms in coverage report. -cvgprecollect Specify a UCDB file as optimization control for the current simulation. This switch can occur multiple times. -cvgprecollectlog Specify the path of the log file where the precollect processing information will be written to. -cvgperinstance Force the option.per_instance control in all covergroup declarations to 1. -cvgsingledefaultbin Collapse a Covergroup default array bin into a scalar bin -cvghaltillbin Halt simulation when an illegal cover/cross bin gets hit -cvgmergeinstances Set the default value of covergroup type_option.merge_instances to 1 -cvgsparsecross Force modelling of Covergroup cross bins in a sparse fashion. -cvgsparsearraybin Force modelling of Covergroup unsize array bins in a sparse fashion. -cvgzwnocollect <1|0> Turn on/off the coverage data collection of zero-weight coverage items. -cvgbintstamp Record simulation timestamp when a covergroup bin is covered during simulation run -cvgopt[=[+|-][,[+|-]]*] Enable Covergroup optimization modes. Valid modes are: minhitcnt - stop sampling coverpoint/cross when it is fully covered. -nocrossautobins[=[uncond|cond]] Avoid generating auto bins in cross coverage computation. -noimplicitcoverpoint Avoid collecting coverage for implicit coverpoints. +autofindloop Find the infinite zero-delay loop when Iteration Limit is exceeded. This option should be used with full design visibility e.g. vopt +acc -hazards Enable hazard checking +initmem+ Specify seed value to be used for randomizing fixed-size arrays marked for randomization by vlog/vopt. +initreg+ Specify seed value to be used for randomizing variables marked for randomization by vlog/vopt. -initreport Report initial values generated due to applying +initreg/+initmem options to vlog/vopt +initregNBA | +noinitregNBA Controls whether +initreg settings applied to registers of sequential UDPs should be non-blocking. This is useful when continuous assignments overwrite register initialization. +initregNBA -- (default) enables this functionality +noinitregNBA -- disables this functionality. +int_delays Optimize annotation of interconnect delays -L Search library for design units instantiated from Verilog and for VHDL default component binding -Lf Same as -L, but libraries are searched before `uselib +maxdelays Use maximum timing from min:typ:max expressions +mindelays Use minimum timing from min:typ:max expressions +no_autodtc Turn off auto-detection of optimized cells with negative timing checks and autoapplication of +delayed_timing_checks to those cells. +no_cancelled_e_msg Disable negative pulse warning messages -noimmedca Revert to pre-6.5 continuous assignment event ordering +no_neg_tchk Set negative timing check limits to zero +no_path_edge Ignore the input edge specification on path delays +no_pulse_msg Disable path pulse error warning messages +nosdferror Treat SDF errors as warnings +nosdfwarn Disable warnings from SDF annotator +no_show_cancelled_e Cancel negative pulse (Default) +nospecify Disable specify path delays and timing checks +notiftoggle01[+] Use the metastable UDP evaluation of enabled Verilog cells in simulation. Default seed value is 0 -no_autoacc Prevents vsim from automatically passing the +acc switch to vopt. -nosva Disable SystemVerilog concurrent assertions -noimmedassert Disable SystemVerilog and VHDL immediate assertions -nocvg Disable Covergroup object construction and builtin calls -nocvgmergeinstances Set the default value of covergroup type_option.merge_instances to 0 -nocvgperinstance Force the option.per_instance control in all covergroup declarations to 0. -nocvgzwopt Enable sampling for zero weight covergroup items -no_risefall_delaynets Disables the rise/fall delay net delay negative timing check algorithm. +nowarnBSOB Disables run-time warning messages for bit-selects in initial blocks that are out of bounds +nowarn Disable specified warning message (Example: +nowarnTFMPC) +ntc_warn Enable warnings from negative timing constraint algorithm +ntcnotchks Disable timing checks while maintaining NTC delays -pli "" Load the list of PLI shared objects -plicompatdefault [latest | 2009 | 2005 | 2001] Specify the VPI object model behavior within vsim. This switch applies globally, not to individual libraries. + Option accessible by PLI routine mc_scan_plusargs +pulse_e/ Set path pulse error limit as percentage of path delay +pulse_e_style_ondetect Drive pulse error state immediately on detection +pulse_e_style_onevent Drive pulse error state on time of pending event (Default) +pulse_int_e/ Set interconnect pulse error limit as percentage of delay +pulse_int_r/ Set interconnect pulse rejection limit as percentage of delay +pulse_r/ Set path pulse rejection limit as percentage of path delay +sdf_iopath_to_prim_ok Prevent vsim from issuing an error when it cannot locate specify path delays to annotate +sdf_nocheck_celltype Disable check between SDF celltype name and module name +show_cancelled_e Drive pulse error state on negative pulse -solvebeforeerrorseverity= Specify error message severity for suppressible errors that are detected in a solve/before constraint Valid values: 0 - no error 1 - warning 2 - error 3 - failure 4 - fatal -solveengine Use specified solver engine to evaluate randomize() scenarios Valid engines - auto, bdd, act -solvefaildebug[=value] Display constraint conflicts on randomize() failure Valid values: 0 - disable solvefaildebug 1 - basic debug (no performance penalty) 2 - enhanced debug (runtime performance penalty) If no value is specified, basic debug will be enabled. -solvefailtestcase[=filename] Upon encountering a randomize() failure, generate a simplified testcase that will reproduce the failure. Optionally output the testcase to the specified file. Testcases for 'no-solution' failures will only be produced if -solvefaildebug is enabled. -solveprofile Enable randomize() profiling (profile data included in solver report) -solverev Specify random sequence compatibility with (Example: -solverev 6.2a) -solvetimeout Specify solver timeout threshold (in seconds). randomize() will fail if the CPU time required to evaluate any randset exceeds the specified timeout. A value of 0 will disable timeout failures. -solveverbose Print information about randomize() call processing -sv_seed Specify a seed for the Random Number Generator (RNG) of the root thread (SystemVerilog) -sva Enable SystemVerilog concurrent assertions -svext[=[+|-][,[+|-]]*] Enable SystemVerilog language extensions. Valid extensions are: cfce - Generate an error if $cast fails as a function. expdfmt - enable certain format string extensions for $display/$sformatf fmtcap - prints hapital hex digits with %X/%H in display calls. iddp - ignore DPI disable protocol check. -tab Specify PLI TAB file -tbxhvllint Enables TBX to identify delays encountered at runtime, with file name line number and the delay maturity time. (This feature depends on libraries that have been compiled with -tbxhvllint specified to vlog) +transport_int_delays Use transport mode for interconnect delays +transport_path_delays Use transport mode for path delays (Default: inertial) +typdelays Use typical timing from min:typ:max expressions (Default) -udpcountlimit [ | 0 ] Limit the number of counts that are tracked for UDP Coverage. -usenonstdcoveragesavesysf Replaces implementation of the built-in, IEEE 1800 compliant system function with the non-standard variant, and thus affects all calls to $coverage_save(). -uvmcontrol=[all,disable,struct,msglog,trlog,certe] Control specific UVM-aware debug options (default: -uvmcontrol=struct) +vlog_retain_on | +vlog_retain_off Enable or disable SDF RETAIN delay processing. +vlog_retain_on is the default behavior. +vlog_retain_same2same_on | +vlog_retain_same2same_off Enable or disable SDF RETAIN delay processing of X insertion on outputs that do not change, but the causal inputs change. +vlog_retain_same2same_on is the default behavior. -v2k_int_delays Use Verilog 2000 style interconnect delays -wreal_resolution [,check|,nocheck ] Specify resolve behavior for AMS wreal net with multiple drivers, where is default, 4state, sum, avg, min, or max. check/nocheck determine if compatibility with nettype real resolution functions is to be checked. -wrealdefaultzero Sets the default value for an undriven wreal net to zero (0). -gconrun/-nogconrun Enable/disable garbage collection after each simulation run command. -gconstep/-nogconstep Enable/disable garbage collection after each step command. -gcthreshold Specify the threshold for Garbage Collection. The default size is 100. (i.e. Garbage Collection will be triggered after every 100M byte of class object allocation.) -------------------------------- SystemC options ------------------------------- -cpppath Specify path to the desired GNU compiler. Use same compiler path as specified on the sccom command line. -cppinstall <[gcc|g++] version> Specify the version of the desired GNU compiler supported and distributed by Mentor. Use same compiler path as specified on the sccom command line. -noautoldlibpath Disable setting of LD_LIBRARY_PATH set internally. -sc22 Use the IEEE 1666-2005 standard (default: IEEE 1666-2011). -sc_arg Specify a SystemC command line argument accessible using sc_main(), sc_argc() and sc_argv() -scdpidebug Turn on debugging for SystemC DPI export function call -sclib Load the SystemC shared library from By default the systemc.so shared library is loaded from the library in which the top level SystemC design unit is compiled. This option should be used when systemc.so is not in the same library as the top level SystemC design unit. -scstacksize Set SystemC thread stack size. The stack size is set as an integer number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or Gb(Giga-byte). Examples: '1000 Kb', '1 Mb', '1 Gb' -noscmainscopename Strip sc_main() scope from the hierarchical path. -valgrind "[options]" Run valgrind in simulation with user given options ------------------------------ Visualizer options ------------------------------ -qwavedb[=+