// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition"

// DATE "04/26/2016 14:42:51"

// 
// Device: Altera EP4CE6E22C6 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (SystemVerilog) only
// 

`timescale 1 ps/ 1 ps

module lab3 (
	reset,
	inclk0_sig);
input 	reset;
input 	inclk0_sig;

// Design Ports Information
// reset	=>  Location: PIN_104,	 I/O Standard: 2.5 V,	 Current Strength: Default
// inclk0_sig	=>  Location: PIN_53,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("lab3_v.sdo");
// synopsys translate_on

wire \reset~input_o ;
wire \inclk0_sig~input_o ;


// Location: IOIBUF_X34_Y18_N1
cycloneive_io_ibuf \reset~input (
	.i(reset),
	.ibar(gnd),
	.o(\reset~input_o ));
// synopsys translate_off
defparam \reset~input .bus_hold = "false";
defparam \reset~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X16_Y0_N1
cycloneive_io_ibuf \inclk0_sig~input (
	.i(inclk0_sig),
	.ibar(gnd),
	.o(\inclk0_sig~input_o ));
// synopsys translate_off
defparam \inclk0_sig~input .bus_hold = "false";
defparam \inclk0_sig~input .simulate_z_as = "z";
// synopsys translate_on

endmodule