Draw the appropriate logic for the following code. Use only D-type FFs, 
muxes, and combinatorial logic.  Label all pins and wires. 

test1: PROCESS(clk, reset_n, in)
  BEGIN
    IF(reset_n = '0') THEN
      out <= '1';
    ELSIF (clk'EVENT AND clk = '1') THEN
      out <= in;
    END IF;
END PROCESS test1;


test2: PROCESS(clk, reset_n)
  BEGIN
    IF(reset_n = '0') THEN
      out <= '0';
    ELSIF (clk'EVENT AND clk = '1') THEN
      out <= NOT out;
    END IF;
END PROCESS test2;

test3: PROCESS(clk, reset_n, in)
  BEGIN
    IF (clk'EVENT AND clk = '1') THEN
      IF (reset_n = '0') THEN
        out <= '0';
      ELSE 
        out <= in;
      END IF;
    END IF;
END PROCESS test3;

test4: PROCESS(clk, in)
  BEGIN
    IF (clk = '1') THEN
      out <= in;
    END IF;
END PROCESS test4;

test5: PROCESS(clk, reset_n, en, in)
  BEGIN
    IF(reset_n = '0') THEN
      out <= '0';
    ELSIF (clk'EVENT AND clk = '1') THEN
      IF (en = '1') THEN
        out <= in;
      END IF;
    END IF;
END PROCESS test5;

test6: PROCESS(clk, reset_n, in)
  BEGIN
    IF(reset_n = '0') THEN
      out  <= '0';
      out1 <= '0';
    ELSIF (clk'EVENT AND clk = '1') THEN
        out  <= in;
        out1 <= out;
    END IF;
END PROCESS test6;