Cadence Tips

This page will be updated slowly.

• Emergency Tips
• Install info
• Composer Tips
  • Making a new library
  • Componsent
  • Wiring
  • Plot
  • Troubleshooting
• Hspice with Cadence Tips
  • Netlist
• Spectre Tips
  • Convergency Problem in DC Operating Points
  • My comments for the Accuracy
• Layout
  • Pin Name
• Extract
  • Join Nets
• Making GDS file
• SCMOS Tips

How can I kill Cadence safely?

Instead of killing cadence immediately, use

% kill -HUP <your process number>

This will give Cadence a break to save all file in a certain way.
How to recover? Read ahead.

CDS deamon

When it happen:

Most likely, after cycling the power on the network

Why it happen:

Cadence deamon doesn't start yet. It should start automatically, but ... you know.

How do I know:

If you get this message in your CDS.log window, the cadence deamon needs to be invoked manually.
*WARNING* XXread: Failed to register lock for file /nfs/pal/apps/cds/tools.hppa/dfII/etc/cdslib/sheets/US_8ths/Bsize/symbol/symbol.cdb-ddLockPath: Lock service on pal is not responding, lockpath is /nfs/pal/apps/cds/tools.hppa/dfII/etc/cdslib/sheets/US_8ths/Bsize/symbol/symbol.cdb

How do I solve:

1. Log into Pal.ECE
2. Check the deamon using "cdsdStatus pal"
3. Invoke the deamon using "cdsd"
4. Check the deamon again, using "cdsStatus pal"

If you get this message, you can use the cadence.

        cdsMonitor      net-version(s)  1
        cdsLock         net-version(s)  1,2

How can I recover my works?

If you follow the above instruction to kill its process, Cadence creates panic.log in your home directly. In that file, you can find the command to recover the each file.

e.g.

Cellview (loopgain schematic) from lib (ThirdOrder) is saved in the panic file
    (/nfs/guille/analog1/k/kaj/AMI/ThirdOrder/loopgain/schematic/sch.cd-)
To recover do:
    dbOpenPanicCellView("ThirdOrder" "loopgain" "schematic")

You can invoke it.

Install directory

Since I don't have an authority for installing Cadence at ECE, I don't have all info and you don't need it, either. But sometimes we need to know where it is installed. For example, Cadence manual (openbook) refers some examples of OCEAN scripts, such as your_install_dir/tools/dfII/samples/artist/OCEAN

Our install directory is:

/nfs/guille/a1/sunapps/cadence/IC4.45/

How can I find the name of the technology file?

If you don't know the name of your technology file, pick one of the provided library and create a technology file from that information.

Technology File -> Dump in icfb Window.
You can name the file as you wish, like hp05.tf, ami12.tf, etc. .

Is there any help manual for each analog components?

I would like to know where it is, indeed!
Please tell me the location when you find it.

How can I connect pins without wires?

For example, clock control pins of switches.

Add -> Wire Name in Composer Window.

You can put labels on the wires and all same labels are connected electrically, even though it's not connected visually.

How can I check if those are connected or not?

Design -> Probe -> Add Net in Composer Window.

You can see all connected wires in high-light, after you click the wire which you want to check it. You can remove this high-light with:

Design -> Probe -> Remove Net or Remove All in Composer Window.

How to plot on-resistance of a switch

Since we need AC analysis to get the on-resistance with bias voltage sweeping, we can draw this test circuit.
Spectre needs several tricks to set the x-axis as a voltage. Here are the steps you may follow.

1. In Analog Artist Simulation window,
   Analysis -> Choose ...
   ac and dc analysis. For ac analysis, you don't need many sweep point because you need just one frequency spot. You need dc analysis, too, since you need proper bias points for x-axis.

2. Do parametric analysis, in Analog Artist Window, to get the resistance for each bias point.
   Tools -> Parametric Analysis ...
   Setup -> Pick Name For Variable
   Pick your bias voltage.
   Analysis -> Start

3. In the calculator, choose Special Functions and specify a certain frequency, say 1 Hz, to get a value at that frequency. Pick reasonable frequency. This function will calculate the interpolation. I will simulate 1Hz to 2Hz for 1Hz step, then plot at 1Hz. This is enough to show the on-resistance.
   

4. Press plot, as usual.
   

How to make EPS file

Design -> Plot -> Submit, then you will get this window.
You may have to uncheck "header" in Plot With area. Then, at the bottom of this window, click Plot Options....
You may choose "Encapsulated PostScript" in Plotter Name and check "Send Plot Only To File". Specify your file name. (in this window I named "opamp1.eps")
Then press OK for both windows. You can include EPS files into your LaTeX documents.

I can't change the transistor number!

In the below Edit Object Properties window, you can't edit the instance name.
Look at the the Apply To field. You selected all selected. You should change it to only current. Then you can change the instance name.

Problem:I can't plot my global node!

Solution: Check your node name. Remove your instance name.

For example, the bias node bp1 is a global node (bp1!) and subcircuit I3 uses this node. When you specify the node thru "Calculator", you will get VT("/I3/bp1!") in the calculator display.
Remove /I3 portion. That means, try VT("/bp1!") to plot it. Even though it's a global node (w/ ! mark), cadence put the instance name and it brings this problem.

This doesn't happen when your top schematic has a global node wire.

I named the node number, but they are different from what I expect!?

Maybe you named the only "number", like "1", "2", ... , "23", ... and so on. If you name the node with some alphabets, like "n1", "n2", ..., "n23", ... and so on, then you will get the correct results in the netlist for Hspice. I don't know why, but I can avoid this problem with this tip.

How to Create a Hspice Netlist

1. Save your schematic. (Very important!)
2. In Composer window, choose Tools -> Analog Artist
   Then you will get this window.
   
   
3. Choose Setup -> Simulation/Directory/Host .... Then you will get this window.
   Change Simulator field to hspiceS as in this picutre. Then click OK.
   
4. Choose Setup -> Environment in the Analog Artist Simulation window. Then you will get this window
   
   Check hspice box in the Include/Stimulus File Syntax field, like this figure. Then click OK.
5. Choose Simulation -> Netlist -> Create Final in the Analog Artist. Then, you will get the result netlist.
6. Save that netlist.

Debug hint

Problem

I had a convergency problem in the op analysis in spectre. It has a macro-modelled common-mode feedback circuits. I doubt this common-mode feedback block. In Hspice the same circuits converges. So the circuits should work. :-(

Solution

I set the node voltage, as well as standard spice technique. It works. In Analog Artist Simulation window, you can set the voltage.

Simulation -> Convergency Aids -> Node Set...

1. Set the voltage in the Node Voltage field.
2. Click the wire in the schematic window.
3. Given voltage value and node name will be appear in the below window.

Bottom line

Gear method is better than others to get higher accuracy, also in Spectre.

More words

% spectre -help tran
(thanks José for this tip)

In it, we can find the accuracy comments as follows:

The `method' parameter specifies the integration method.  The possible settings
and their meanings are:
`method=euler':      Backward-Euler is used exclusively.
`method=traponly':   Trapezoidal rule is used almost exclusively.
`method=trap':       Backward-Euler and the trapezoidal rule are used.
`method=gear2only':  Gear's second-order backward-difference method is used
                     almost exclusively.
`method=gear2':      Backward-Euler and second-order Gear are used.
`method=trapgear2':  Allows all three integration methods to be used.
The trapezoidal rule is usually the most efficient when you want high accuracy.
This method can exhibit point-to-point ringing, but you can control this by
tightening the error tolerances.  For this reason, though, if you choose very
loose tolerances to get a quick answer, either backward-Euler or second-order
Gear will probably give better results than the trapezoidal rule.  Second-order
Gear and backward-Euler can make systems appear more stable than they really
are.  This effect is less pronounced with second-order Gear or when you request
high accuracy.

Several parameters determine the accuracy of the transient analysis. `reltol'
and `abstol' control the accuracy of the discretized equation solution. These
parameters determine how well charge is conserved and how accurately steady-
state or equilibrium points are computed.  You can set the integration error,
or the errors in the computation of the circuit dynamics (such as time
constants), relative to `reltol' and `abstol' by setting the `lteratio'
parameter. 

The parameter `relref' determines how the relative error is treated.  The
`relref' options are:
`relref=pointlocal': Compares the relative errors in quantities at each node to
                     that node alone.
`relref=alllocal':   Compares the relative errors at each node to the largest
                     values found for that node alone for all past time.
`relref=sigglobal':  Compares relative errors in each of the circuit signals to
                     the maximum for all signals at any previous point in
                     time.
`relref=allglobal':  Same as `relref=sigglobal' except that it also compares
                     the residues (KCL error) for each node to the maximum of
                     that node's past history.
The `errpreset' parameter lets you adjust the simulator parameters to fit your
needs quickly.  You can set `errpreset' to `conservative' if the circuit is
very sensitive, or you can set it to `liberal' for a fast. but possibly
inaccurate, simulation. The setting `errpreset=moderate' suits most needs.

The effect of `errpreset' on other parameters is shown in the following table.
In this table, `T'= `stop' - `start'.
errpreset      reltol  relref     method      maxstep       lteratio
--------------------------------------------------------------------
liberal        * 10    allglobal  gear2       Interval/10   3.5
moderate               sigglobal  traponly    Interval/50   3.5
conservative   * 0.1   alllocal   gear2only   Interval/100  10.0

The value of `reltol' is increased or decreased from its value in the options
statement, but it is not allowed to be larger than 0.01. Spectre sets the value
of `maxstep' so that it is no larger than the value given in the table. Except
for `reltol' and `maxstep', `errpreset' does not change the value of any
parameters you have explicitly set. The actual values used for the transient
analysis are given in the log file.

If the circuit you are simulating can have infinitely fast transitions (for
example, a circuit that contains nodes with no capacitance), Spectre might have
convergence problems. To avoid this, you must prevent the circuit from
responding instantaneously.  You can accomplish this by setting `cmin', the
minimum capacitance to ground at each node, to a physically reasonable nonzero
value. This often significantly improves Spectre convergence.

Spectre provides two methods for reducing the number of output data points
saved: `strobing', based on the simulation time, and `skipping' time points,
which saves only every N'th point. 

The parameters `strobeperiod' and `strobedelay' control the strobing
method.`strobeperiod' sets the interval between points that you want to save,
and `strobedelay' sets the offset within the period relative to `skipstart'.
The simulator forces a time step on each point to be saved, so the data is
computed, not interpolated. 

The skipping method is controlled by `skipcount'. If this is set to N, then
only every N'th point is saved.

The parameters `skipstart' and `skipstop' apply to both data reduction methods.
Before `skipstart' and after `skipstop', Spectre saves all computed data.  

If you do not want any data saved before a given time, use `outputstart'. If
you do not want any data saved after a given time, change the `stop' time.

Option -> Display
Check the box of Pin Names.

When you want to connect more than two nodes, you may want to connect outside of the cell. Then, you have to tell Cadence that those should be connected later. It is the time when you extract the layout.

Check the Join Nets With Same Name box.

1. In CDS window,
   File -> Export -> Stream
2. Fill in the "Library Name"
3. Fill in the "Top Cell Name" : this is the name of your cell view.
4. Fill in the "Output File"
5. Fill in the "View name" as "layout", if it is not there.
6. Click "User-Defined Data"
7. Fill in the "Layer Map Table" file
8. Press "OK"

This page is link-free.
Any comments are welcome.
Tetsuya Kajita

Last modified: Wed Aug 15 11:58:04 2001