ECE 599: Phase Lock Loop 2 (Advance Clocking Techniques)

Announcements:

03/29/2015: Project proposal due by April 20, 2016.
03/29/2015: Project report due by June 3, 2016.

Course Syllabus: (download pdf)

Instructor:

Tejasvi Anand (anandt@eecs.oregonstate.edu)
Office: KEC 4113, Ph: 541-737-4673
Office Hours : Friday, 4:00-5:00pm (or by appointment)
Location : KEC 4113

Lectures:

Class Location: GBAD 103
Class Time : 10:00-10:50am, Monday, Wednesday and Friday

Prerequisites:

ECE 599 PLL-1 (or prior PLL, DLL, MDLL, MILO, or CDR design experience)

Research Papers (For Discussion):

Digital PLLs

• P. K. Hanumolu, G. Y. Wei, U. K. Moon and K. Mayaram, “Digitally-Enhanced Phase-Locking Circuits,” in Proc. of IEEE CICC, Sep. 2007, pp. 361-368.

• P. H. Hsieh, J. Maxey, C. K. K. Yang, “A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology,” in IEEE J. Solid State Circuits, vol. 45, no. 4, pp. 781-792, Apr. 2010.

• J. A. Tierno, A. V. Rylyakov, D. J. Friedman, “A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI,” in IEEE J. Solid State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008.

• A. Rylyakov, J. Tierno, H. Ainspan, J. O. Plouchart, J. Bulzacchelli, Z. T. Deniz and D. Friedman, “Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications,” in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 94-95.

• W. Yin, R. Inti, A. Elshazly, B. Young and P. K. Hanumolu, “A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking,” in IEEE J. Solid State Circuits, vol. 46, no. 8, pp. 1870-1880, Aug. 2011.

Supply Noise Insensitive PLLs

• M. Mansuri and C. K. K. Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” in IEEE J. Solid State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003.

• T. Wu, K. Mayaram and U. K. Moon, “An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators,” in IEEE J. Solid State Circuits, vol. 42, no. 4, pp. 775-783, Apr. 2007.

• A. Elshazly, R. Inti, W. Yin, B. Young and P. K. Hanumolu, “A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration,” in IEEE J. Solid State Circuits, vol. 46, no. 12, pp. 2759-2771, Dec. 2011.

• Y. C. Huang, C. F. Liang, H. S. Huang and P. Y. Wang, “A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO,” in ISSCC Dig. Tech. Papers, Feb. 2014, pp. 270-271.

• C. W. Yeh, C. E. Hsieh and S. I. Liu, “A 3.2GHz digital phase-locked loop with background supply-noise cancellation,” in ISSCC Dig. Tech. Papers, Feb. 2016, pp. 332-333.

Small Area PLLs

• W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada and A. Matsuzawa, “A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique,” in IEEE J. Solid State Circuits, vol. 50, no. 1, pp. 68-80, Jan. 2015.

• J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim, and P. K. Hanumolu, “A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2016, pp. 338-340.

Low Noise PLLs

• X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N ^{2},” in IEEE J. Solid State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.

• X. Gao, E. A. M. Klumperink, G. Socci, M. Bohsali and B. Nauta, “Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector,” in IEEE J. Solid State Circuits, vol. 45, no. 9, pp. 1809-1821, Sep. 2010.

• L. Kong and B. Razavi, “A 2.4GHz 4mW inductorless RF synthesizer,” in ISSCC Dig. Tech. Papers, Feb. 2015, pp. 450-451.

• Z. Huang, B. Jiang, L. Li and H. C. Luong, “A 4.2us-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL,” in ISSCC Dig. Tech. Papers, Feb. 2016, pp. 40-41.

Digital CDRs

• J. L. Sonntag and J. Stonick, “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links,” in IEEE J. Solid State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006.

Fractional-N PLLs

Misc PLLs

• B. Razavi, “The Role of PLLs in Future Wireline Transmitters,” in Trans. Circuits Syst. I, vol. 56, no. 8, pp. 1786-1793, Aug. 2009.

• R. B. Staszewski et. al, “All-digital PLL and transmitter for mobile phones,” in IEEE J. Solid State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. 2005.

• V. Kratyuk, P. K. Hanumolu, U. K. Moon and K. Mayaram, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” in Trans. Circuits Syst. II, vol. 54, no. 3, pp. 247-251, Mar. 2007.

Textbooks:

No textbook is required.

Reference Books:

• F. Gardner, Phase lock Techniques, John Wiley & Sons, 2005.

• D. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall, 1991.

• W. Egan, Phase-Lock Basics, John Wiley & Sons, 1998.

• R. Best, Phase-Locked Loops: Design, Simulation, and Applications, McGraw Hill, 2003.

• B. Razavi, RF Microelectronics, Pearson, 2014