ECE 599: Phase Lock Loop 2 (Advance Clocking Techniques)

Announcements:

04/2/2017: No lecture on Monday, April 3 2017.
04/2/2017: Project proposal due by May 1, 2017.
04/2/2017: Project report due by June 5, 2017.

Course Syllabus: (download pdf)

Instructor:

Tejasvi Anand (anandt@eecs.oregonstate.edu)
Office: KEC 4113, Ph: 541-737-4673
Office Hours : Friday, 4:00-5:00pm (or by appointment)
Location : KEC 4113

Lectures:

Class Location: STAG 261
Class Time : 10:00-10:50am, Monday, Wednesday and Friday

Prerequisites:

ECE 599 PLL-1 (or prior PLL, DLL, MDLL, MILO, or CDR design experience)

Research Papers (For Discussion):

Digital PLLs

Supply Noise Insensitive PLLs

Small Area PLLs

Low Noise PLLs

Fast Power-on Lock Clock Multipliers for Rapid On/Off Operation

Clock and Data Recovery Circuits

Fractional-N PLLs

Misc PLLs

Textbooks:

No textbook is required.

Reference Books:

  • F. Gardner, Phase lock Techniques, John Wiley & Sons, 2005.

  • D. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall, 1991.

  • W. Egan, Phase-Lock Basics, John Wiley & Sons, 1998.

  • R. Best, Phase-Locked Loops: Design, Simulation, and Applications, McGraw Hill, 2003.

  • B. Razavi, RF Microelectronics, Pearson, 2014