👤 About Me

I received the B.Sc. and M.Sc. degrees in Electrical and Electronics Engineering from Shamsipour Institute of Technology and the University of Tehran, Iran, respectively, in 2014 and 2017. My undergraduate program concluded with me achieving the highest GPA among all students in the class of 2010, and my master’s program at the University of Tehran, was where I first developed a deep interest in circuit design. Motivated to expand this interest into the realm of high-speed mixed-signal integrated circuits (IC), I began my doctoral studies in Electronics at Oregon State University, Corvallis, Oregon, USA, in 2021.

I am currently a Ph.D. student in Professor Tejasvi Anand’s research group, where my research focuses on exploring novel mixed-signal IC designs and system-level architectures for next-generation high-speed wireline communication systems, with a particular emphasis on enhancing energy efficiency. Since 2022, I have been a Research Scholar with the Center for Ubiquitous Connectivity (CUbiC) sponsored by Semiconductor Research Corporation (SRC), where I work on machine learning-inspired wireline links architectures. I also serve as a reviewer for the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

During my PhD, I have been actively involved in various design projects and chip tapeouts. My first chip, a PAM-4 transceiver for medium-reach wireline links, was designed in 16nm FinFET technology and employed artificial intelligence (AI) principles through on-chip classifiers. It achieved 2x improvement in energy efficiency compared to conventional transceivers and was recognized with the Best Student Paper Award at the 2025 IEEE Custom Integrated Circuits Conference (CICC). My second chip extended this machine learning–based wireline approach to standard NRZ signaling by introducing an on-chip random forest classifier for long-reach applications (47dB) and was presented at 2025 Symposium on VLSI Technology and Circuits.