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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| 474_assn2_rubric.ods | 2007-05-25 17:17 | 9.8K | |
| AjayBavleDFT_lecture_slides.ppt | 2006-01-24 08:13 | 6.2M | |
| Digital_Design_Using_SystemVerilog.pptx | 2011-05-01 12:26 | 522K | |
| FPGA_prototype_method_manual_.pdf | 2011-03-30 13:20 | 13M | |
| Fpro_osu.pdf | 2007-02-23 09:24 | 321K | |
| Jex_Dike.pdf | 2005-11-21 16:14 | 631K | |
| SAED_Cell_Lib_Rev1_4_20_1.pdf | 2009-05-21 06:53 | 1.9M | |
| Signetics_AN219.pdf | 2005-11-21 16:08 | 35K | |
| VerilogHDL(1).ppt | 2008-04-16 17:25 | 1.2M | |
| Verilog_X_Bugs.pdf | 2010-04-18 21:28 | 402K | |
| keeping_the_clock_pure.pdf | 2008-02-29 10:32 | 292K | |
| synth_script_multi_clk_designs.pdf | 2003-05-02 16:47 | 217K | |
| tas_doc.pdf | 2011-04-29 09:04 | 25K | |
| x_in_simulation.pdf | 2004-04-16 16:02 | 632K | |