(CICC 2019) Equalizer Free Communication For Bandwidth Limited Channels

We present an alternative strategy for communicating on bandwidth limited wireline channels *without* using conventional equalizers (FFE, DFE, CTLE): Dicode encoding, ISI error correction and decoding. Compared to the state-of-the-art Viterbi-based transceivers, the proposed transceiver achieves 4x better energy efficiency, 3x higher data rate, and 30x lower latency.

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(CICC 2019) Source + Switched Capacitor Harvester with No Top and Bottom Plate Switching Loss

We present a new switching technique, which helps to break the trade-off between switching loss and charge redistribution loss in a switched capacitor. The proposed switching avoids charging and discharging of top and bottom plate parasitic capacitors. As a result, the energy lost in switching the top and bottom plate parasitic capacitors is zero joules.

Template 1

(ISSCC 2018) Clock Domain Equalization using iPWM Encoding for Low Voltage Wireline Links

Low voltage transceiver equalization is a challenge. We propose clock domain equalization (signal processing) based wireline transceiver architecture. In the proposed transceiver, equalization is performed in the subrate clock at very-low bandwidth, which helps to equalize heavy channel loss even at 0.5V supply. Our transceiver operates from 0.5-to-0.9V (3-to-16Gb/s) and equalize 27dB Loss at 10Gb/s (1.8pJ/bit).

(ISSCC 2017) A New Line-Coding Scheme for Energy Efficient Equalization - Integrated Pulse Width Modulation (iPWM)

We invented a new line-coding scheme to efficiently equalize lossy wireline channels. The proposed encoding scheme is demonstrated on a 10-18Gb/s wireline transceiver using 65nm CMOS. Operating at 16Gb/s, the complete transceiver achieves an energy efficiency of 4.37pJ/bit and can equalize 27dB channel loss.

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(ISSCC 2017, JSSC 2015) A 7Gb/s Embedded Clock Transceiver for Energy Proportional Links

We developed architecture and circuit techniques to achieve rapid-on/off in PLL, transmitter and receiver. The proposed transceiver demonstrates power scalability and energy proportional operation with a wide range of link utilization. This transceiver can power-on and lock in less than 20ns.

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(ISSCC 2013, JSSC 2014) A 5Gb/s, 10ns Power-On-Time, 36μW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links

We developed the transmitter with digital regulators and MDLL based clock to achieve rapid-on/off oepration. By using highly digital architecture the 2.5GHz MDLL achieves power-on-lock in 10ns (3 reference cycles).

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(VLSI 2015, JSSC 2016) A VCO Based Highly Digital Temperature Sensor with 0.034oC/mV Supply Sensitivity

We developed a self-referenced VCO-based temperature sensor with reduced supply sensitivity in 65nm CMOS. A novel sensing technique is proposed in which temperature information is acquired by evaluating the ratio of the output frequencies of two ring oscillators.

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Research Thrust

We investigate efficient communication and harvesting systems. Our research focus is on wireline communication systems, energy harvesters, sensors for IoT, and frequency synthesizers (PLLs, MDLLs, MILOs) with special emphasis on energy efficiency. Details of ongoing and completed research projects can be found here.

Open Ph.D. Positions (2020) - 1

If you are interested in solving challenging research problems then please email me your CV (E-mail: anandt@eecs.oregonstate.edu).



News and Updates

May 2019: Our work on 12-to-39.6Gb/s PAM-8 wireline trasceiver is accepted in ESSCIRC 2019. Congratulations Yusang Chun!

March 2019: Prof. Tejasvi Anand became a member of CICC TPC.

March 2019: Wireline transceiver with data encoding and sequence detection based decoding paper is nominated for the best student paper award. Congratulations Yusang Chun!

March 2019: A webinar on "Line-Coding Based Equalization Techniques For High Speed SerDes" will be presented by Prof. Tejasvi Anand on March 13 (10 AM PST). Registration can be done using: this link: http://go.mentor.com/55fBV

January 2019: Our sub 1uW switched capacitor based energy harvester paper is accepted in CICC 2019. Congratulations Mohamed Megahed!

January 2019: Our wireline transceiver with data encoding and sequence detection based decoding paper is accepted in CICC 2019. Congratulations Yusang Chun!

September 2018: Abhishekh Devaraj successfully defended his M.S. thesis. Congratulations! He will be joining Skyworks in Irvine, CA.

April 2018: Kamila Almurzayeva and Natalie Clouse joined the MSCS lab.

April 2018: Zhiping Wang joined the MSCS lab.

October 2017: Our paper on low-voltage wireline transceiver with encoding based clock domain equalization has been accepted in the ISSCC 2018. Congratulations Ashwin!

September 2017: Mohamed M. Mabrouk joined the MSCS lab.

August 2017: Ashwin Ramachandran successfully defended his M.S. thesis. Congratulations! He will be joining Texas Instruments.

January 2017: Ashwin Ramachandran won the prestigious Analog Devices Outstanding Student Designer Award. Congratulations Ashwin!

January 2017: Our paper on DSM-free spread-spectrum PLL has been accepted in the CICC 2017. Congratulations Hyuk Sun (Tim)!

December 2016: Our paper on VCO based highly digital temperature sensor is third most popular article in JSSC during November.

December 2016: Hyuk Sun (Tim) successfully defended his thesis. Congratulations Tim!

October 2016: Our paper on 16Gb/s wireline transceiver with phase domain equalization has been accepted in the ISSCC 2017. Congratulations Ashwin!

August 2016: Yu Sang Chun and Abhishekh Devaraj joined the MSCS lab.

March 2016: Ashwin Ramachandran joined the MSCS lab.

Contact Details

School of EECS,
4113 Kelley Engineering Center,
Corvallis, OR 97331-5501
Phone: (541) 737-4673
Fax: (541) 737-1300
E-mail: anandt@eecs.oregonstate.edu