2023
[C1] V. Vesley, C. Y. Lee, T. Anand, and U-K. Moon, "PLL-SAR: A new high-speed analog to digital converter architecture," in Proc. IEEE Int. Midwest Symposium on Circuits and Systems (MWCAS), Aug. 2023.[J1] M. Megahed and T. Anand, "A Sub-uW energy harvester architecture with reduced top/bottom plate switching loss achieving 80.66% peak efficiency in 180-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 58, no. 5, pp. 1386-1399, May 2023.
2022
[C1] X. Lin, M. Megahed, and T. Anand, “A single-clock-phase sense amplifier architecture with 9x smaller clock-to-Q delay compared to the StrongARM & 6.3dB lower noise compared to Double-Tail,” in Proc. IEEE Symp. VLSI Circuits, June 2022.[J1] Y. Chun, M. Megahed, A. Ramachandran and T. Anand, “A PAM-8 wireline transceiver with linearity improvement technique and a time-domain receiver side FFE in 65 nm CMOS,” IEEE Journal of Solid-State Circuits , vol. 57, no. 5, pp. 1527-1541, May 2022.
2021
[C1] Z. Wang, M. Megahed, Y. Chun, and T. Anand, “A machine learning inspired transceiver with ISI-resilient data encoding: Hybrid-Ternary coding + 2-tap FFE + CTLE + feature extraction and classification for 44.7dB channel loss in 7.3pJ/bit,” in Proc. IEEE Symp. VLSI Circuits, June 2021.[C2] M. Megahed, Y. Chun, Z. Wang, and T. Anand, “A 27 Gb/s 8-ary modulated wireline transceiver using pulse width and amplitude modulation achieving 9.5 dB SNR improvement over PAM-8 with 5.39 pJ/bit,” in Proc. IEEE Symp. VLSI Circuits, June 2021.
[J1] S. Bose, T. Anand, and M.L. Johnston, "A 3.5-mV input single-inductor self-starting boost converter with loss-aware MPPT for efficient autonomous body-heat energy harvesting," IEEE Journal of Solid-State Circuits , vol. 56, no. 6, pp. 1837-1848, June 2021.
2020
[J1] A. Ramachandran, Y. Chun, M. Megahed and T. Anand, "An iPWM line-coding based wireline transceiver with clock domain encoding for compensating up to 27dB loss while operating at 0.5-to-0.9V and 3-to-16Gb/s in 65nm CMOS," IEEE Journal of Solid-State Circuits vol. 55, no. 7, pp. 1946-1959, July. 2020.[J2] Y. Chun and T. Anand, "An ISI-resilient data encoding for equalizer-free wireline communication - Dicode encoding and error correction for 24.2dB loss with 2.56pJ/bit," IEEE Journal of Solid-State Circuits vol. 55, no. 3, pp. 567-579, Mar. 2020.
[J3] H. Sun, K. Sobue, K. Hamashita, T. Anand and U. Moon, "A 951-fsrms period jitter 3.2% modulation range in-band modulation spread-spectrum clock generator," IEEE Journal of Solid-State Circuits vol. 55, no. 2, pp. 426-438, Feb. 2020.
2019
[C1] Y. Chun, A. Ramachandran, and T. Anand, “A PAM-8 wireline transceiver with receiver side PWM (time-domain) feed forward equalization operating from 12-to-39.6Gb/s in 65nm CMOS,” in Proc. IEEE European Solid State Circuits Conf. (ESSCIRC), Sep. 2019, pp. 1-4.[C2] T. Anand, “A Stochastic Wireline Communication System,” in Proc. IEEE Int. Midwest Symposium on Circuits and Systems (MWCAS), Aug. 2019.
[C3] Y. Chun and T. Anand, “A 13.6-16Gb/s wireline transceiver with dicode encoding and sequence detection decoding for equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2019, pp. 1-4. [Nominated for the best student paper award]
[C4] M. Megahed, Y. Ramadas, and T. Anand, “A sub 1μW switched source + capacitor architecture free of top/bottom plate parasitic switching loss achiving peak efficiency of 80.66% at a regulated 1.8V output in 180nm,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2019, pp. 1-4.
[C5] S. Bose, T. Anand, and M. Johnston, “A 3.5 mV input, 82% peak efficiency boost converter with loss-optimized MPPT and 50 mV integrated cold-start for thermoelectric energy harvesting,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2019, pp. 1-4.
[J1] A. Ramachandran, A. Natarajan and T. Anand, "Line coding techniques for channel equalization: integrated pulse-width modulation and consecutive digit chopping," IEEE Transactions on Circuits and Systems I vol. 66, no. 3, pp. 1192-1204, Mar. 2019.
[J2] S. Bose, T. Anand, and M.L. Johnston, "Integrated cold-start of a boost converter at 57mV using cross-coupled complementary charge pumps and ultra-low-voltage ring oscillator," IEEE Journal of Solid-State Circuits vol. 54, no. 10, pp. 2867-2878, Oct. 2019.
[J3] A. Devaraj, M. Megahed, Y. Liu, A. Ramachandran, and T. Anand, "A switched capacitor multiple input single output energy harvester (solar + piezo) achieving 74.6% efficiency with simultaneous MPPT," IEEE Transactions on Circuits and Systems I vol. 66, no. 12, pp. 4876-4887, Sep. 2019.
2018
[C1] S. Bose, T. Anand, and M.L. Johnston, "Fully-Integrated 57 mV Cold Start of a Thermoelectric Energy Harvester using a Cross-Coupled Complementary Charge Pump," in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2018, pp. 1-4.[C2] A. Ramachandran and T. Anand, “A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/bit wireline transceiver equalizing 27dB loss at 10Gb/s with clock domain encoding: integrated pulse width modulation (iPWM) in 65nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, Feb. 2018. pp. 376-377.
[J1] Bodhisatwa Sadhu, Tejasvi Anand, and Scott K. Reynolds, "A fully decoupled LC tank VCO topology for amplitude boosted low phase noise operation," IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2488-2499, Sept. 2018.
[J2] D. Wei, T. Anand, G. Shu, J. E. Schutt-Ainé and P. K. Hanumolu, "A 10-Gb/s/ch, 0.6-pJ/bit/mm power scalable rapid-on/off transceiver for on-chip energy proportional interconnects," IEEE J. Solid-State Circuits, vol. 53, no. 3, pp. 873-883, Mar 2018.
2017
[C1] H. Sun, K. Sobue, K. Hamashita, T. Anand, and U-K Moon, “A 0.951psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2017, pp. 1-4.[C2] K. Zhan, A. Agrawal, M. Johnson, A. Ramachandran, T. Anand, and A. Natarajan, “An integrated 7-Gb/s 60-GHz communication link over single conductor wire using sommerfeld wave propagation in 65-nm CMOS,” in Proc. IEEE MTT-S Int. Microwave Symp. (IMS) , Jun. 2017, pp. 797-800. [Nominated for the best student paper award]
[C3] A. Ramachandran, A. Natarajan, and T. Anand, “A 16Gb/s, 3.6pJ/bit wireline transceiver with phase domain equalization scheme: integrated pulse width modulation (iPWM) in 65nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017. pp. 488-489.
[J1] M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana, S. Saxena, B. Young, W-S. Choi, P. Hanumolu, “A 5 GHz digital fractional-N PLL using a 1-bit delta-sigma frequency-to-digital converter in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no 9, pp. 2306-2319, Sep. 2017.
[J2] S. Saxena, G. Shu, R. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W-S. Choi, P. Hanumolu, “A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver," IEEE J. Solid-State Circuits, vol. 52, no 5, pp. 1399-1411, May. 2017.
2016
[J1] T. Anand, Kofi A. A. Makinwa, and P. Hanumolu, “A VCO based highly digital temperature sensor with 0.034oC/mV supply sensitivity," IEEE J. Solid-State Circuits, vol. 51, no 11, pp. 2651-2663, Nov. 2016.[J2] G. Shu, W-S. Choi, S. Saxena, M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, and P. K. Hanumolu, "A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition," IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016.
-------Prior to OSU-------
2015
[C1] T. Anand, K. Makinwa, and P. Hanumolu, “A self-referenced VCO based temperature sensor with 0.034oC/mV supply sensitivity in 65nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2015, pp. C200–C201.[C2] S. Saxena, G. Shu, R. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S-J. Kim, W-S. Choi, and P. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun 2015, pp. C352-C353.
[C3] T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. Hanumolu, “A 7Gb/s rapid on/off embedded clock serial link transceiver with 20ns power-on time, 740μW off-state power for energy proportional links in 65nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. pp. 64-65.
[C4] A. Elkholy, M. Talegaonkar, T. Anand, and P. Hanumolu, “A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015. pp. 188-189.
[J1] T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena A. Elshazly, and P. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,” IEEE J. Solid-State Circuits, vol. 50, no 12, pp. 3101-3119, Dec. 2015.
[J2] A. Elkholy, M. Talegaonkar, T. Anand and P. Kumar Hanumolu, "Design and analysis of low-power high-frequency robust sub-harmonic injection-locked clock multipliers," IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3160-3174, Dec. 2015.
[J3] A. Elkholy, T. Anand, W-S. Choi, A. Elshazly, and P. Hanumolu, “A 3.7mW low-noise wide-bandwidth 4.5GHz digital fractional-N PLL using time amplifier-based TDC,” IEEE J. Solid-State Circuits , vol. 50, no 4, pp. 867-881, Apr. 2015.
[J4] R. Nandwana, T. Anand, S. Saxena, S-J. Kim, M. Talegaonkar, A. Elkholy, W-S. Choi, A. Elshazly, and P. Hanumolu, “A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method,” IEEE J. Solid-State Circuits, vol. 50, no 4, pp. 882-895, Apr. 2015.
[J5] W-S. Choi, T. Anand, G. Shu, and P. Hanumolu, “A burst-mode digital receiver with programmable input jitter filtering for energy proportional links,” IEEE J. Solid-State Circuits, vol 50, no 3, pp. 737-748, Mar 2015.
2014
[C1] M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. Nandwana, S. Saxena, B. Young, W-S. Choi, and P. Hanumolu, “A 4.4-5.4GHz digital fractional-N PLL using frequency-to-digital converter,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2014, pp. 1-2.[C2] R. Nandwana, T. Anand, S. Saxena, S-J. Kim, M. Talegaonkar, A. Elkholy, W-S. Choi, A. Elshazly, and P. Hanumolu, “A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2014, pp. 1-2.
[C3] A. Elkholy, T. Anand, W-S. Choi, A. Elshazly, and P. Hanumolu, “A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz in-band noise using time amplifier based TDC,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2014, pp. 1-2.
[C4] B. Young, K. Reddy, S. Rao, A. Elshazly, T. Anand, and P. Hanumolu, “A 75dB DR 50MHz BW 3rd order CT-Δ∑ modulator using VCO-based integrators”, in Proc. IEEE Symp. VLSI Circuits, Jun. 2014, pp. 1-2.
[C5] G. Shu, W-S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 150-151.
[J1] T. Anand, A. Elshazly, M. Talegaonkar, B. Young, and P. Hanumolu, “A 5Gb/s, 10ns power-on-time, 36μW off-state power, fast power-on transmitter for energy proportional links,” IEEE J. Solid-State Circuits, vol. 49, no 10, pp. 2243-2258, Oct. 2014.
[J2] M. Talegaonkar, A. Elshazly, K. Reddy, P. Prabha, T. Anand, and P. Hanumolu, “An 8Gb/s-64Mb/s, 2.3-4.2mW/Gb/s burst-mode transmitter in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no 10, pp. 2228-2242, Oct. 2014.
2013
[C1] W-S. Choi, T. Anand, G. Shu, and P. Hanumolu, “A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering”, in Proc. IEEE Symp. VLSI Circuits, Jun. 2013, pp. C280-C281.[C2] T. Anand, M. Talegaonkar, A. Elshazly, B. Young, and P. Hanumolu, “A 2.5GHz 2.2mW/25μW on/off-state power 2psrms long-term-jitter digital clock multiplier with 3-reference cycles power-on time,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp. 256-257.
[J1] V. Chaturvedi, T. Anand and B. Amrutur, “An 8-to-1 bit 1-MS/s SAR ADC with VGA and integrated data compression for neural recording,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 21, no. 11, pp. 2034-2044, Nov. 2013.