Journal Papers    Conference Papers    Graduate Thesis    Miscellaneous
     

    1. M. Li, C.Y. Lee, P.K. Venkatachala, A. ElShater, Y. Miyahara, K. Sobue, K. Tomioka, and U. Moon, "A rail-to-rail 12MS/s 91.3dB SNDR 94.1dB DR two-step SAR ADC with integrated input buffer using predictive level-shifting," IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 12, pp. 3555-3564, Dec. 2023.
       
    2. G. Temes, U. Moon, and D. Allstot, "Switched-capacitor circuits," IEEE Circuits Syst. Magazine, vol. 21, no. 4, pp. 40-42, Nov. 2021.
       
    3. L. Shi, E. Thaigarajan, R. Singh, E. Hancioglu, U. Moon, and G. Temes, "Noise-shaping SAR ADC using a two-capacitor digitally calibrated DAC with 82.6dB SNDR and 90.9dB SFDR," IEEE Trans. Circuits Syst. I (TCAS1). vol. 68, no. 10, pp. 4001-4012, Oct. 2021.
       
    4. C.Y. Lee, P.K. Venkatachala, A. ElShater, and U. Moon, "A pseudo-pseudo-differential ADC achieving 105dB SNDR in 10kHz bandwidth using ring amplifier based integrators," IEEE Trans. Circuits Syst. II (TCAS2), vol. 68, no. 7, pp. 2327-2331, Jul. 2021.
       
    5. Y. Xu, H. Hu, J. Muhlestein, and U. Moon, "A 77-dB-DR 0.65-mW 20-MHz 5th-order coupled source followers based low-pass filter," IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 10, pp. 2810-2918, Oct. 2020.
       
    6. H. Sun, K. Sobue, K. Hamashita, T. Anand, and U. Moon, "A 951-fsrms period jitter 3.2% modulation range in-band modulation spread-spectrum clock generator," IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 2, pp. 426-438, Feb. 2020.
       
    7. Y. Xu, P.K. Venkatachala, Y. Hu, S. Leuenberger, G. Temes, and U. Moon, "A charge-domain switched-Gm-C band-pass filter using interleaved semi-passive charge-sharing technique," IEEE Trans. Circuits Syst. I (TCAS1), vol. 67, no. 2, pp. 600-610, Feb. 2020.
       
    8. A. ElShater, P.K. Venkatachala, C.Y. Lee, J. Muhlestein, S. Leuenberger, K. Sobue, K. Hamashita, and U. Moon, "A 10mW 16b 15MS/s two-step SAR ADC with 95dB DR using dual-deadzone ring amplifier," IEEE J. Solid-State Circuits (JSSC), vol. 54, no. 12, pp. 3410-3420, Dec. 2019.
       
    9. T. He, M. Kareppagoudr, Y. Zhang, E. Caceres, U. Moon, and G. Temes, "Noise filtering and linearization of single-ended sampled-data circuits," IEEE Trans. Circuits Syst. I (TCAS1), vol. 66, no. 4, pp. 1331-1341, Apr. 2019.
       
    10. H. Sun, K. Sobue, K. Hamashita, and U. Moon, "An oversampling stochastic ADC using VCO-based quantizers," IEEE Trans. Circuits Syst. I (TCAS1), vol. 65, no. 12, pp. 4037-4050, Dec. 2018.
       
    11. Y. Xu and U. Moon, "A chopper-stabilized source follower coupling based low-pass filter with noice reduction," Analog Int. Circuits Sig. Proc., vol. 95, no. 2, pp. 365-369, May 2018.
       
    12. A. Waters, J. Muhlestein, and U. Moon, "Analysis of metastability errors in conventional, LSB-first, and asynchronous SAR ADCs," IEEE Trans. Circuits Syst. I (TCAS1), vol. 63, no. 11, pp. 1898-1909, Nov. 2016.
       
    13. Y. Xu and U. Moon, "Charge-domain switched-gm-C CBPF using semi-passive charge-sharing technique," Electron. Lett. (EL), vol. 52, no. 20, pp. 1667-1669, Sep. 29, 2016.
       
    14. Y. Hu, H. Venkatram, N. Maghari, and U. Moon, "A continuous-time delta-sigma ADC utilizing time information for two cycles of excess loop delay compensation," IEEE Trans. Circuits Syst. II (TCAS2), vol. 62, no. 11, pp. 1063-1067, Nov. 2015.
       
    15. M. Gande, H. Venkatram, H. Lee, J. Guerber, and U. Moon, "Blind calibration algorithm for nonlinearity correction based on selective sampling," IEEE J. Solid-State Circuits (JSSC), vol. 49, no. 8, pp. 1715-1724, Aug. 2014.
       
    16. T. Oh, H. Venkatram, and U. Moon, "A time-based pipelined ADC using both voltage and time domain information," IEEE J. Solid-State Circuits (JSSC), vol. 49, no. 4, pp. 961-971, Apr. 2014.
       
    17. S. Weaver, B. Hershberg, and U. Moon, "Digitally synthesized stochastic flash ADC using only standard digital cells," IEEE Trans. Circuits Syst. I (TCAS1), vol. 61, no. 1, pp. 84-91, Jan. 2014.
       
    18. H. Venkatram, J. Guerber, M. Gande, and U. Moon, "Detection and correction method for single event effects in analog to digital converters," IEEE Trans. Circuits Syst. I (TCAS1), vol. 60, no. 12, pp. 3163-3172, Dec. 2013.
       
    19. T. Oh, N. Maghari, and U. Moon, "A second-order delta-sigma ADC using noise-shaped two-step integrating quantizer," IEEE J. Solid-State Circuits (JSSC), vol. 48, no. 6, pp. 1465-1474, Jun. 2013.
       
    20. J. Guerber, H. Venkatram, M. Gande, and U. Moon, "A ternary R2R DAC designed for improved energy efficiency," Electron. Lett. (EL), vol. 49, no. 5, pp. 329-330, Feb. 28, 2013.
       
    21. O. Rajaee and U. Moon, "Highly linear noise-shaped pipelined ADC utilizing a relaxed accuracy front-end," IEEE J. Solid-State Circuits (JSSC), vol. 48, no. 2, pp. 502-515, Feb. 2013.
       
    22. B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon, "Ring ampfliers for switched capacitor circuits," IEEE J. Solid-State Circuits (JSSC), vol. 47, no. 12, pp. 2928-2942, Dec. 2012.
       
    23. J. Guerber, H. Venkatram, M. Gande, A. Waters, and U. Moon, "A 10-b ternary SAR ADC with quantization time information utilization," IEEE J. Solid-State Circuits (JSSC), vol. 47, no. 11, pp. 2604-2613, Nov. 2012.
       
    24. S. Weaver, B. Hershberg, P. Hanumolu, and U. Moon, "A multiplexer-based digital passive linear counter (PLINCO)," Analog Int. Circuits Sig. Proc., vol. 73, no. 1, pp. 143-149, Oct. 2012.
       
    25. N. Sasidhar, D. Gubbins, P. Hanumolu, and U. Moon, "Rail-to-rail input pipelined ADC incorporating multistage signal mapping," IEEE Trans. Circuits Syst. II (TCAS2), vol. 59, no. 9, pp. 558-562, Sep. 2012.
       
    26. J. Guerber, M. Gande, and U. Moon, "The analysis and application of redundant multistage ADC resolution improvements through PDF residue shaping," IEEE Trans. Circuits Syst. I (TCAS1), vol. 59, no. 8, pp. 1733-1742, Aug. 2012.
       
    27. N. Maghari and U. Moon, "A third-order delta-sigma modulator using noise-shaped bi-directional single-slop quantizer," IEEE J. Solid-State Circuits (JSSC), vol. 46, no. 12, pp. 2882-2891, Dec. 2011.
       
    28. S. Weaver, B. Hershberg, N. Maghari, and U. Moon, "Domino-logic-based ADC for digital synthesis," IEEE Trans. Circuits Syst. II (TCAS2), vol. 58, no. 11, pp. 744-747, Nov. 2011.
       
    29. O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, "Low-OSR over-ranging hybrid ADC incorporating noise-shaped two-step quantizer," IEEE J. Solid-State Circuits (JSSC), vol. 46, no. 11, pp. 2458-2468, Nov. 2011.
       
    30. T. Oh, N. Maghari, D. Gubbins, and U. Moon, "Analysis of residue integration sampling with improved jitter immunity," IEEE Trans. Circuits Syst. II (TCAS1), vol. 58, no. 7, pp. 417-421, Jul. 2011.
       
    31. I. Vytyaz, P. Hanumolu, U. Moon, and K. Mayaram, "Design-oriented analysis of circuits with equality constraints," IEEE Trans. Circuits Syst. I (TCAS1), vol. 58, no. 5, pp. 1089-1098, May 2011.
       
    32. T. Musah and U. Moon, "Correlated level shifting integrator with reduced sensitivity to amplifier gain," Electron. Lett. (EL), vol. 47, no. 2, pp. 91-92, Jan. 29, 2011.
       
    33. B. Hershberg, S. Weaver, and U. Moon, "Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp," IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 12, pp. 2623-2633, Dec. 2010.
       
    34. S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, and U. Moon, "Stochastic flash analog-to-digital conversion," IEEE Trans. Circuits Syst. I (TCAS1), vol. 57, no. 11, pp. 2825-2833, Nov. 2010.
       
    35. D. Gubbins, B. Lee, P. Hanumolu, and U. Moon, "Continuous-time input pipeline ADCs," IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 8, pp. 1456-1468, Aug. 2010.
       
    36. Y. Hu, N, Maghari, T. Musah, and U. Moon, "Time-interleaved noise-shaping integrating quantisers," Electron. Lett. (EL), vol. 46, no. 11, pp. 757-758, May 27, 2010.
       
    37. H. Venkatram, J. Guerber, S. Lee, and U. Moon, "Merged capacitor switching based SAR ADC with highest switching energy-efficiency," Electron. Lett. (EL), vol. 46, no. 9, pp. 620-621, Apr. 29, 2010.
       
    38. O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, "Design of a 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC," IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 719-730, Apr. 2010.
       
    39. C. Peach, U. Moon, and D. Allstot, "A 11.1mW 42MS/s 10b ADC with two-step settling in 0.18um CMOS," IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 2, pp. 391-400, Feb. 2010.
       
    40. N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, "A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback," IEEE J. Solid-State Circuits (JSSC), vol. 44, no. 9, pp. 2392-2401, Sep. 2009.
       
    41. M. Kim, P. Hanumolu, and U. Moon, "A 10MS/s 11-b 0.19mm^2 algorithmic ADC with improved clocking scheme," IEEE J. Solid-State Circuits (JSSC), vol. 44, no. 9, pp. 2348-2355, Sep. 2009.
       
    42. V. Kratyuk, P. Hanumolu, K. Ok, U. Moon, and K. Mayaram, "A digital PLL with a stochastic time-to-digital converter," IEEE Trans. Circuits Syst. I (TCAS1), vol. 56, no. 8, pp. 1612-1621, Aug. 2009.
       
    43. N. Maghari, S. Kwon, and U. Moon, "74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB open-loop opamp gain," IEEE J. Solid-State Circuits (JSSC), vol. 44, no. 8, pp. 2212-2221, Aug. 2009.
       
    44. T. Musah and U. Moon, "Correlated level shifting technique with cross-coupled gain-enhancement capacitors," Electron. Lett. (EL), vol. 45, no. 13, pp. 672-674, Jun. 18, 2009.
       
    45. N. Maghari, G. Temes, and U. Moon, "Noise-shaped integrating quantizers in delta-sigma modulators," Electron. Lett. (EL), vol. 45, no. 12, pp. 612-613, Jun. 4, 2009.
       
    46. I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Automated design and optimization of low-noise oscillators," IEEE Trans. Computer-Aided Design (TCAD), pp. 609-622, May 2009.
       
    47. K. Lee, Q. Meng, T. Sugimoto, K. Hamashita, K. Takasuka, K. Takeuchi, U. Moon, and G. Temes, "A 0.8V, 2.6mW 88dB dual-channel audio delta-sigma D/A converter with headphone driver," IEEE J. Solid-State Circuits (JSSC), vol. 44, no. 3, pp. 916-927, Mar. 2009.
       
    48. T. Wu, P. Hanumolu, K. Mayaram, and U. Moon, "Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers," IEEE J. Solid-State Circuits (JSSC), vol. 44, no. 2, pp. 427-435, Feb. 2009.
       
    49. N. Maghari, G. Temes, and U. Moon, "Single-loop delta-sigma modulator with extended dynamic range," Electron. Lett. (EL), vol. 44, no. 25, pp. 1452-1453, Dec. 4, 2008.
       
    50. B.R. Gregoire and U. Moon, "An over-60dB true rail-to-rail performance using correlated level shifting and an opamp with only 30dB loop gain," IEEE J. Solid-State Circuits (JSSC), vol. 43, no. 12, pp. 2620-2630, Dec. 2008.
       
    51. I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity analysis for oscillators," IEEE Trans. Computer-Aided Design (TCAD), pp. 1521-1534, Sep. 2008.
       
    52. M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, "A 0.9V 92dB doubled-sampled switched-RC delta-sigma audio ADC," IEEE J. Solid-State Circuits (JSSC), vol. 43, no. 5, pp. 1195-1206, May 2008.
       
    53. P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon, "A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter," IEEE J. Solid-State Circuits (JSSC), vol. 43, no. 2, pp. 414-424, Feb. 2008.
       
    54. P. Hanumolu, G. Wei, and U. Moon, "A wide-tracking range clock and data recovery circuit," IEEE J. Solid-State Circuits (JSSC), vol. 43, no. 2, pp. 425-439, Feb. 2008.
       
    55. T. Musah, B.R. Gregoire, E. Naviasky, and U. Moon, "Parallel correlated double sampling technique for pipelined analogue-to-digital converters," Electron. Lett. (EL), vol. 43, no. 23, Nov. 8, 2007.
       
    56. P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon, "Design of low-voltage highly linear switched-R-MOSFET-C filters," IEEE J. Solid-State Circuits (JSSC), vol. 42, no. 8, pp. 1699-1709, Aug. 2007.
       
    57. R. Wang, S. Kim, S. Lee, S. You, J. Kim, U. Moon, and G. Temes, "A 100-dB gain-corrected delta-sigma audio DAC with headphone driver," Analog Int. Circuits Sig. Proc., vol. 51, no. 1, pp. 27-31, Apr. 2007.
       
    58. T. Wu, K. Mayaram, and U. Moon, "An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators," IEEE J. Solid-State Circuits (JSSC), vol. 42, no. 4, pp. 775-783, Apr. 2007.
       
    59. B.R. Gregoire and U. Moon, "A sub 1-V constant Gm-C switched-capacitor current source," IEEE Trans. Circuits Syst. II (TCAS2), vol. 54, no. 3, pp. 222-226, Mar. 2007.
       
    60. V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy," IEEE Trans. Circuits Syst. II (TCAS2), vol. 54, no. 3, pp. 247-251, Mar. 2007.
       
    61. V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "Frequency detector for fast frequency lock of digital PLLs," Electron. Lett. (EL), vol. 43, no. 1, pp. 13-14, Jan. 4, 2007.
       
    62. M. Brownlee, P. Hanumolu, K. Mayaram, and U. Moon, "A 0.5-GHz to 0.5-GHz PLL with fully differential supply regulated tuning," IEEE J. Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2720-2728, Dec. 2006.
       
    63. N. Maghari, S. Kwon, G. Temes, and U. Moon, "Sturdy MASH delta-sigma modulator," Electron. Lett. (EL), vol. 42, no. 22, pp. 1269-1270, Oct. 26, 2006.
       
    64. J. Li, U. Moon, J. McNeill, M. Coln, and B. Larivee, "Comments on "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC," (correspondence letter) IEEE J. Solid-State Circuits (JSSC), vol. 41, no. 6, pp. 1481, Jun. 2006.
       
    65. G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita, K. Takasuka, G. Temes, and U. Moon, "A 0.6V 82dB delta-sigma audio ADC using switched-RC integrators," IEEE J. Solid-State Circuits (JSSC), vol. 40, no. 12, pp. 2398-2407, Dec. 2005.
       
    66. A. Pulincherry, M. Hufford, E. Naviasky, and U. Moon, "A time-delay jitter insensitive continuous-time bandpass delta-sigma modulator architecture," IEEE Trans. Circuits Syst. II (TCAS2), pp. 680-684, Oct. 2005.
       
    67. P. Hanumolu, G. Wei, and U. Moon, "Equalizers for high-speed serial links," Int. J. High Speed Elec. Syst., vol. 15, no. 2, pp. 429-458, Jun. 2005 (also published as a book chapter).
       
    68. G. Vemulapalli, P. Hanumolu, Y. Kook, and U. Moon, "A 0.8V, accurately tuned, linear continuous-time filter," IEEE J. Solid-State Circuits (JSSC), vol. 40, no. 9, pp. 1972-1977, Sep. 2005.
       
    69. B. Greenley, R. Veith, D. Chang, and U. Moon, "A low-voltage 10-bit CMOS DAC in 0.01 mm2 die area," IEEE Trans. Circuits Syst. II (TCAS2), pp. 246-250, May 2005.
       
    70. V. Sharma, A. Narayanan, T. Rengachari, G. Temes, F. Chaplen, and U. Moon, "A low-cost, portable generic biotoxicity assay for environmental monitoring applications," Biosensors and Bioelectronics, vol. 20/11, pp. 2218-2227, May 2005.
       
    71. J. Li, G. Ahn, D. Chang, and U. Moon, "A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR," IEEE J. Solid-State Circuits (JSSC), vol. 40, no. 4, pp. 960-969, Apr. 2005.
       
    72. A. Rao, W. McIntyre, U. Moon, and G. Temes, "Noise shaping techniques applied to switched capacitor voltage regulators," IEEE J. Solid-State Circuits (JSSC), vol. 40, no. 2, pp. 422-429, Feb. 2005.
       
    73. D. Chang, G. Ahn, and U. Moon, "Sub-1V design techniques for high-linearity multi-stage/pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I (TCAS1), pp. 1-12, Jan. 2005.
       
    74. D. Chang, J. Li, and U. Moon, "Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs," IEEE Trans. Circuits Syst. I (TCAS1), pp. 2133-2140, Nov. 2004.
       
    75. P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, "Analysis of charge-pump phased-locked loops," IEEE Trans. Circuits Syst. I (TCAS1), pp. 1665-1674, Sep. 2004.
       
    76. J. Li and U. Moon, "A 1.8V 67mW 10b 100MS/s pipelined ADC using time-shifted CDS technique," IEEE J. Solid-State Circuits (JSSC), vol. 39, no. 9, pp. 1468-1476, Sep. 2004.
       
    77. S. Yoo, J. Park, S. Lee, and U. Moon, "A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching," IEEE Trans. Circuits Syst. II (TCAS2), pp. 269-275, May 2004.
       
    78. C. Myers, B. Greenley, D. Thomas, and U. Moon, "Continuous-time filter design optimized for reduced die area," IEEE Trans. Circuits Syst. II (TCAS2), pp. 105-110, Mar. 2004.
       
    79. U. Moon and G. Huang, "CMOS implementation of nonlinear spectral-line timing recovery in digital data-communication systems," IEEE Trans. Circuits Syst. I (TCAS1), pp. 298-308, Feb. 2004.
       
    80. P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon, "Analysis of PLL clock jitter in high-speed serial links," IEEE Trans. Circuits Syst. II (TCAS2), pp. 879-886, Nov. 2003.
       
    81. J. Li and U. Moon, "Background calibration techniques for multi-stage pipelined ADCs with digital redundancy," IEEE Trans. Circuits Syst. II (TCAS2), pp. 531-538, Sep. 2003.
       
    82. D. Chang and U. Moon, "A 1.4-V 10-bit 25MSPS pipelined ADC using opamp-reset switching technique," IEEE J. Solid-State Circuits (JSSC), vol. 38, no. 8, pp. 1401-1404, Aug. 2003.
       
    83. Y Qu, N. Barton, R. Fetche, N. Seshan, T. Fiez, U. Moon, and K. Mayaram, "Phase noise simulation and estimation methods: a comparative study," IEEE Trans. Circuits Syst. II (TCAS2), pp. 635-638, Sep. 2002.
       
    84. T. Kajita, U. Moon, and G. Temes, "A two-chip interface for a MEMS accelerometer," IEEE Trans. Inst. Meas., vol. 51, no. 4, pp. 853-858, Aug. 2002.
       
    85. M. Keskin, U. Moon, and G. Temes, "A 1-V, 10-MHz clock-rate, 13-bit CMOS delta-sigma modulator," IEEE J. Solid-State Circuits (JSSC), vol. 37, no. 7, pp. 817-824, Jul. 2002.
       
    86. T. Kajita, U. Moon, G. Temes, "A noise-shaping accelerometer interface circuit for two-chip implementation," VLSI Design, pp. 355-361, Jun. 2002.
       
    87. U. Moon, K. Mayaram, and J. Stonick, "Spectral analysis of time-domain phase jitter measurements," IEEE Trans. Circuits Syst. II (TCAS2), pp. 321-327, May 2002.
       
    88. M. Keskin, U. Moon, and G. Temes, "Direct-charge-transfer pseudo-N-path SC circuit insensitive to the element mismatch and opamp nonidealities," Analog Int. Circuits Sig. Proc., vol. 30, no. 3, pp. 243-247, Mar. 2002.
       
    89. J. Silva, U. Moon, J. Steensgaard, and G. Temes, "A wideband low-distortion delta-sigma ADC topology," Electron. Lett. (EL), vol. 37, no. 12, pp. 737-738, Jun. 7, 2001.
       
    90. D. Chang and U. Moon, "1-V input sampling circuit with improved linearity," Electron. Lett. (EL), vol. 37, no. 8, pp. 479-481, Apr. 8, 2001.
       
    91. X. Wang, P. Kiss, U. Moon, J. Steensgaard, and G. Temes, "Digital estimation and correction of DAC errors in multibit delta-sigma ADCs," Electron. Lett. (EL), vol. 37, no. 7, pp. 414-415, Mar. 29, 2001.
       
    92. M. Keskin, U. Moon, and G. Temes, "Switched-capacitor resonator structure with improved performance," Electron. Lett. (EL), vol. 37, no. 4, pp. 212-213, Feb. 15, 2001.
       
    93. T. Kajita, G. Temes, and U. Moon, "Correlated double sampling integrator insensitive to parasitic capacitance," Electron. Lett. (EL), vol. 37, no. 3, pp. 151-153, Feb. 1, 2001.
       
    94. P. Kiss, U. Moon, J. Steensgaard, J. Stonick, and G. Temes, "High-speed delta-sigma ADC with error correction," Electron. Lett. (EL), vol. 37, no. 2, pp. 76-77, Jan. 18, 2001.
       
    95. W. Wilson, U. Moon, K. Lakshmikumar, and L. Dai, "A CMOS self-calibrating frequency synthesizer," IEEE J. Solid-State Circuits (JSSC), vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
       
    96. P. Kiss, J. Silva, A. Wiesbauer, T. Sun, U. Moon, J. Stonick, and G. Temes, "Adaptive digital correction of analog errors in MASH ADCs - Part II. Correction using test-signal injection," IEEE Trans. Circuits Syst. II (TCAS2), pp. 629-638, Jul. 2000.
       
    97. U. Moon, "CMOS high-frequency switched-capacitor filters for telecommunication applications," IEEE J. Solid-State Circuits (JSSC), vol. 35, no. 2, pp. 212-220, Feb. 2000.
       
    98. U. Moon, J. Silva, J. Steensgaard, and G. Temes, "Switched-capacitor DAC with analog mismatch correction," Electron. Lett. (EL), vol. 35, no. 22, pp. 1903-1904, Oct. 28, 1999.
       
    99. U. Moon, J. Steensgaard, and G. Temes, "Digital techniques for improving the accuracy of data converters," IEEE Comm. Magazine, pp. 136-143, Oct. 1999.
       
    100. J. Steensgaard, U. Moon, and G. Temes, "Mismatch-shaping switching for two-capacitor DAC," Electron. Lett. (EL), vol. 34, no. 17, pp. 1633-1634, Aug. 20, 1998.
       
    101. U. Moon and B. Song, "Background digital calibration techniques for pipelined ADCs," IEEE Trans. Circuits Syst. II (TCAS2), pp. 102-109, Feb. 1997.
       
    102. U. Moon and B. Song, "Design of a low-distortion 22-kHz 5th-order Bessel filter," IEEE J. Solid-State Circuits (JSSC), vol. 28, no. 12, pp. 1254-1264, Dec. 1993.

     

    Conference Papers    Journal Papers    Graduate Thesis    Miscellaneous
     

    1. H. Wang, F. Adin, U. Moon, and G. Temes, "Wideband low-distortion noise-coupled delta-sigma ADC," IEEE Midwest Symp. Circuits Syst. (MWSCAS), Aug. 2024.
       
    2. M. Li, R. Gao, C. Wilson, A. Basak, E. Markwell, M. Johnston, and U. Moon, "An easy-to-drive discrete-time ADC topology using digital predictive level-shifting," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2024.
       
    3. V. Vesely, C.Y. Lee, T. Anand, and U. Moon, "PLL-SAR: A new high-speed analog to digital converter architecture," IEEE Midwest Symp. Circuits Syst. (MWSCAS), Aug. 2023.
       
    4. M. Li, C.Y. Lee, H. Wang, G. Temes, and U. Moon, "A 16-bit 100kHz bandwidth pseudo-pseudo-differential delta-sigma ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2023.
       
    5. M. Li, C.Y. Lee, A. ElShater, Y. Miyahara, K. Sobue, K. Tomioka, and U. Moon, "A rail-to-rail 12MS/s 91.3dB SNDR 94.1dB DR two-step SAR ADC with integrated input buffer using predictive level-shifting," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 172-173, Feb. 2023.
       
    6. H. Hu, V. Vesely, and U. Moon, "Passive third order continuous-time delta-sigma modulator with Q enhancement technique," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2022.
       
    7. H. Hu, V. Vesely, and U. Moon, "Ultra-Low OSR calibration free MASH noise shaping SAR ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2022.
       
    8. D. Allstot, U. Moon, and G. Temes, "Switched-capacitor circuits," invited tutorial, IEEE Custom Int. Circuits Conf. (CICC), Apr. 2022.
       
    9. C.Y. Lee and U. Moon, "A 0.0375mm^2 203.5uW 108.8dB DR DT single-loop DSM audio ADC using a single-ended ring-amplifier-based integrator in 180nm CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 412-413, Feb. 2022.
       
    10. A. Pierce, E. Thaigarajan, R. Singh, E. Hancioglu, U. Moon, and G. Temes, "Low-distortion correlated level shifting sample-and-hold stage," IEEE Northeast Workshop Circuits Syst. (NEWCAS), Jun. 2021.
       
    11. L. Shi, E. Thaigarajan, R. Singh, E. Hancioglu, U. Moon, and G. Temes, "Noise-shaping SAR ADC using a two-capacitor digitally calibrated DAC with 85.1dB DR and 91dB SFDR," IEEE Midwest Symp. Circuits Syst. (MWSCAS), Aug. 2020.
       
    12. B. Xiao, P.K. Venkatachala, Y. Xu, A. ElShater, C.Y. Lee, S. Leuenberger, Q.A. Khan, and U. Moon, "An 80mA capacitor-less LDO with 6.5uA quiescent current and no frequency compensation using adaptive-deadzone ring amplifier," IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2019.
       
    13. C.Y. Lee, A. EIShater, P.K. Venkatachala, H. Hu, B. Xiao, and U. Moon, "Application of ring-amplifiers for low-power wide-bandwidth digital subsampling ADC-PLL," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2019.
       
    14. H. Hu, C.Y. Lee, A. ElShater, Z. Dai, F. Ye, and U. Moon, "Simultaneous STF and NTF estimation in CTDS modulators with ARMA-model," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2019.
       
    15. C.Y. Lee, P.K. Venkatachala, A. EIShater, B. Xiao, H. Hu, and U. Moon, "Cascoded ring amplifiers for high speed and high accuracy settling," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2019.
       
    16. A. ElShater, C.Y. Lee, P.K. Venkatachala, M. Dessouky, and U. Moon, "Gm-free Assisted Opamp Technique for Continuous time Delta-Sigma modulators," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2019.
       
    17. A. ElShater, C.Y. Lee, P.K. Venkatachala, J. Muhlestein, S. Leuenberger, K. Sobue, K. Hamashita, and U. Moon, "A 10mW 16b 15MS/s two-step SAR ADC with 95dB DR using dual-deadzone ring-amplifier," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 70-71, Feb. 2019. (Jack Kilby Best Student Paper Award)
       
    18. S. Leuenberger, P.K. Venkatachala, A. ElShater, M. Oatman, C.Y. Lee, B. Xiao, and U. Moon, "An empirical study of the settling performance of ring amplifiers for pipelined ADCs," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2018.
       
    19. P.K. Venkatachala, S. Leuenberger, A. ElShater, C.Y. Lee, J. Muhlestein, B. Xiao, M. Oatman, and U. Moon, "Passive compensation for improved settling and large signal stabilization of ring amplifiers," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2018.
       
    20. P.K. Venkatachala, S. Leuenberger, A. ElShater, C.Y. Lee, Y. Xu, B. Xiao, M. Oatman, and U. Moon, "Process invariant biasing of ring amplifiers using deadzone regulation circuit," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2018.
       
    21. C.Y. Lee, S. Leuenberger, P.K. Venkatachala, A. ElShater, M. Oatman, B. Xiao, and U. Moon, "A power efficient SAR algorithm for high resolution ADCs," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2018.
       
    22. B Xiao, S. Leuenberger, P.K. Venkatachala, A. ElShater, C.Y. Lee, M. Oatman, and U. Moon, "Power optimized comparator selecting method For stochastic ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), May 2018.
       
    23. T. He, M. Kareppagoudr, Y. Zhang, U. Moon, and G. Temes, "Pseudo-pseudo differential circuits," IEEE Midwest Symp. Circuits Syst. (MWSCAS), pp. 1517-1520, Aug. 2017.
       
    24. J. Muhlestein, F. Farahbakhshian, P.K. Venkatachala, and U. Moon, "A multi-path ring amplifier with dynamic biasing," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1621-1624, May 2017.
       
    25. P.K. Venkatachala, A. El-Shater, Y. Xu, M. El-Chammas, and U. Moon, "Voltage domain correction technique for timing skew errors in time interleaved ADCs," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1432-1435, May 2017.
       
    26. Y. Xu, P.K. Venkatachala, and U. Moon, "A highly compact wideband continuous-time transimpedance low-pass filter," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1625-1628, May 2017.
       
    27. J. Muhlestein, S. Leuenberger, H. Sun, Y. Xu, and U. Moon, "A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization," IEEE Custom Int. Circuits Conf. (CICC), May 2017.
       
    28. S. Leuenberger, J. Muhlestein, H. Sun, P.K. Venkatachala, and U. Moon, "A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier," IEEE Custom Int. Circuits Conf. (CICC), May 2017.
       
    29. H. Sun, K. Sobue, K. Hamashita, T. Anand, and U. Moon, "A 0.951 ps rms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL," IEEE Custom Int. Circuits Conf. (CICC), May 2017.
       
    30. Y. Xu, J. Muhlestein, and U. Moon, "A 0.65mW 20MHz 5th-order low-pass filter with +28.8dBm IIP3 using source follower coupling," IEEE Custom Int. Circuits Conf. (CICC), May 2017.
       
    31. C. Myers, S. Leuenberger, A. ElShater, and U. Moon, "A design for a 6-bit ENOB 20GHz input bandwidth ADC operating at 40Gs/s in 0.18um SiGe BiCMOS," Gov. Microcir. Apps. Critical Tech. Conf. (GOMAC), May 2017.
       
    32. H. Sun, J. Muhlestein, S. Leuenberger, K. Sobue, K. Hamashita, and U. Moon, "A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 325-328, Nov. 2016.
       
    33. D. Robertson, A. Buchwald, M. Flynn, H. Lee, U. Moon, and B. Murmann, "Data converter reflections: 19 papers from the last ten years that deserve a second look," IEEE European Solid-State Circuits Conf. (ESSCIRC), pp. 161-164, Sep. 2016.
       
    34. Y. Xu, S. Leuenberger, P.K. Venkatachala, and U. Moon, "A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18um CMOS," IEEE Symp. VLSI Circuits (VLSI), pp. 132-133, Jun. 2016.
       
    35. Y. Xu, P.K. Venkatachala, S. Leuenberger, and U. Moon, "A 7.5mW 35-70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS," IEEE Radio Freq. Int. Circuits Symp. (RFIC), pp. 162-165, May 2016.
       
    36. H. Sun, K. Sobue, K. Hamashita, and U. Moon, "A power efficient PLL with in-loop-bandwidth spread-spectrum modulation using a charge-based discrete-time loop filter," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2755-2758, May 2016.
       
    37. H. Sun, J. Muhlestein, and U. Moon, "A VCO-based spatial averaging stochastic ADC," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 272-275, Dec. 2015.
       
    38. A. Waters, J. Mushlestein, and U. Moon, "Analysis of metastability errors in asynchronous SAR ADCs," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 547-550, Dec. 2015.
       
    39. J. Muhlestein, H. Venkatram, J. Guerber, A. Waters, and U. Moon, "Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 421-424, Dec. 2015.
       
    40. A. Waters and U. Moon, "A fully automated Verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 69-72, Nov. 2015.
       
    41. Y. Xu, H. Sun, and U. Moon, "Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency," IEEE Midwest Symp. Circuits Syst. (MWSCAS), pp. 109-112, Aug 2015.
       
    42. H. Sun and U. Moon, "MDLL/PLL dual-path clock generator," IEEE Midwest Symp. Circuits Syst. (MWSCAS), pp. 197-200, Aug 2015.
       
    43. A. Waters and U. Moon, "Practical modeling of comparator metastability for conventional and LSB-first SAR ADCs," IEEE Midwest Symp. Circuits Syst. (MWSCAS), pp. 49-52, Aug 2015.
       
    44. Y. Xu, S. Leuenberger, and U. Moon, "Highly linear continuous-time MASH delta-sigma ADC with dual VCO-based quantizers," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2033-2036, May 2015.
       
    45. S. Leuenberger and U. Moon, "A single opamp 2nd-order delta-sigma ADC with a double integrating quantizer," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 309-312, May 2015.
       
    46. Y. Hu, S. Leuenberger, Y. Xu, and U. Moon, "Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2249-2252, May 2015.
       
    47. J. Leung, A. Waters, and U. Moon, "Selectable starting bit SAR ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1654-1657, May 2015.
       
    48. A. Waters, J. Leung, M. Gande, and U. Moon, "A delta-sigma ADC using an LSB-first SAR quantizer," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1638-1641, May 2015.
       
    49. S. Leuenberger, A. Waters, and U. Moon, "Resistive correction of low output impedance high-speed current-steering DACs," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 459-462, Dec. 2014.
       
    50. A. Waters, J. Leung, and U. Moon, "LSB-first SAR ADC with bit-repeating for reduced energy consumption," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 203-206, Dec. 2014.
       
    51. A. Waters, S. Leuenberger, and U. Moon, "Analysis and performance trade-offs of linearity calibration for stochastic ADCs," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 207-210, Dec. 2014.
       
    52. N. Maghari and U. Moon, "Emerging analog-to-digital converters," IEEE European Solid-State Circuits Conf. (ESSCIRC), pp. 43-50, Sep. 2014.
       
    53. Y. Hu, Y. Xu, and U. Moon, "Inherently linear time symmetric pulse width modulation," IEEE Custom Int. Circuits Conf. (CICC), Sep. 2014.
       
    54. H. Venkatram, T. Oh, K. Sobue, K. Hamashita, and U. Moon, "A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using dynamic amplifier," IEEE Symp. VLSI Circuits (VLSI), pp. 37-38, Jun. 2014.
       
    55. F. Farahbakhshian, A. Waters, J. Muhlestein, and U. Moon, "Stochastic approximation register ADC," IEEE Northeast Workshop Circuits Syst. (NEWCAS), pp. 189-192, Jun. 2014 (Best Paper Award).
       
    56. Y. Hu, F. Farahbakhshian, and U. Moon, "Time amplifiers based on phase accumulation," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2349-2352, Jun. 2014.
       
    57. B. Hershberg and U. Moon, "The ring amplifier: scalable amplification with ring oscillators," Workshop on Advances in Analog Circuit and Design (AACD), Apr. 2014 (also published as a Springer book chapter).
       
    58. M. Gande, H. Lee, H. Venkatram, and U. Moon, "Blind background calibration of harmonic distortion based on selective sampling," IEEE Custom Int. Circuits Conf. (CICC), Sep. 2013.
       
    59. H. Venkatram, B. Hershberg, T. Oh, M. Gande, K. Sobue, K. Hamashita, and U. Moon, "Parallel gain enhancement technique for switched-capacitor circuits," IEEE Custom Int. Circuits Conf. (CICC), Sep. 2013.
       
    60. T. Oh, H. Venkatram, and U. Moon, "A 70MS/s 69.3dB SNDR 38.2fJ/conversion-step time-based pipelined ADC," IEEE Symp. VLSI Circuits (VLSI), pp. 96-97, Jun. 2013.
       
    61. B. Hershberg and U. Moon, "A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC," IEEE Symp. VLSI Circuits (VLSI), pp. 94-95, Jun. 2013.
       
    62. M. Gande, J. Guerber, and U. Moon, "Analysis of back-end flash in a 1.5b/stage pipelined ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2247-2250, May 2013.
       
    63. M. Gande, N. Maghari, T. Oh, and U. Moon, "A 71dB dynamic rage third-order delta-sigma TDC using charge-pump," IEEE Symp. VLSI Circuits (VLSI), pp. 168-169, Jun. 2012.
       
    64. T. Oh, N. Maghari, and U. Moon, "A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based delta-sigma ADC," IEEE Symp. VLSI Circuits (VLSI), pp. 162-163, Jun. 2012.
       
    65. B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon, "A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers," IEEE Symp. VLSI Circuits (VLSI), pp. 32-33, Jun. 2012.
       
    66. B. Hershberg, T. Musah, S. Weaver, and U. Moon, "The effect of correlated level shifting on noise performance in switched capacitor circuits," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 942-945, May 2012.
       
    67. H. Venkatram, T. Oh, J. Guerber, and U. Moon, "Class-A+ amplifier with controlled positive feedback for discrete-time signal processing circuits," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 428-431, May 2012.
       
    68. J. Guerber, H. Venkatram, T. Oh, and U. Moon, "Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2361-2364, May 2012.
       
    69. T. Oh, H. Venkatram, J. Guerber, and U. Moon, "Correlated jitter sampling for jitter cancellation in pipelined TDC," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 810-813, May 2012.
       
    70. B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon, "Ring amplifier for switched-capacitor circuits," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 460-461, Feb. 2012.
       
    71. H. Lee, B. Lee, and U. Moon, "A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13um CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 474-475, Feb. 2012.
       
    72. J. Guerber, M. Gande, H. Venkatram, A. Waters, and U. Moon, "A 10b ternary SAR ADC with decision time quantization based redundancy," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 65-68, Nov. 2011.
       
    73. B.R. Gregoire, T. Musah, N. Maghari, S. Weaver, and U. Moon, "A 30% beyond Vdd signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 345-348, Nov. 2011.
       
    74. H. Lee, D. Gubbins, B. Lee, and U. Moon, "A 0.7V 810uW 30MS/s comparator-based two-step pipelined ADC," IEEE Custom Int. Circuits Conf. (CICC), Sep. 2011.
       
    75. S. Weaver, B. Hershberg, and U. Moon, "Digitally synthesized stochastic flash ADC using only standard digital cells," IEEE Symp. VLSI Circuits (VLSI), pp. 266-267, Jun. 2011.
       
    76. O. Rajaee and U. Moon, "A 12-ENOB 6X-OSR noise-shaped pipelined ADC utilizing a 9-bit linear front-end," IEEE Symp. VLSI Circuits (VLSI), pp. 34-35, Jun. 2011.
       
    77. B. Hershberg, S. Weaver, S. Takeuchi, K. Hamashita, and U. Moon, "Binary Access Memory: An optimized lookup table for successive approximation applications," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1620-1623, May 2011.
       
    78. N. Maghari and U. Moon, "A third-order DT delta-sigma modulator using noise-shaped bidirectional single-slope quantizer," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 474-475, Feb. 2011.
       
    79. H. Venkatram, R. Inti, and U. Moon, "Least mean square calibration method for VCO non-linearity," IEEE Int. Conf. Microelec. (ICM), pp. 1-4, Dec. 2010.
       
    80. S. Weaver, B. Hershberg, and U. Moon, "ENOB calculation for ADCs with input-correlated quantization error using a sine-wave test," IEEE Int. Conf. Microelec. (ICM), pp. 5-8, Dec. 2010.
       
    81. H. Venkatram, B. Hershberg, and U. Moon, "Asynchronous CLS for zero crossing based circuits," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 1025-1028, Dec. 2010.
       
    82. S. Weaver, B. Hershberg, and U. Moon, "PDF folding for stochastic flash ADCs," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 770-773, Dec. 2010.
       
    83. O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, "A 1.2V, 78dB HDSP ADC with 3.1V input signal range," IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2010.
       
    84. N. Maghari, S. Weaver, and U. Moon, "A +5dBFS third-order extended dynamic range single-loop delta-sigma modulator," IEEE Custom Int. Circuits Conf. (CICC), Sep. 2010.
       
    85. T. Musah and U. Moon, "Pseudo-differential zero-crossing-based circuits with differential error suppression," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1731-1734, May 2010.
       
    86. O. Rajaee, Y. Hu, M. Gande, and U. Moon, "An interstage correlated double sampling technique for switched-capacitor gain stages," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1252-1255, May 2010.
       
    87. N. Maghari and U. Moon, "Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 297-300, May 2010.
       
    88. N. Maghari and U. Moon, "A double-sampled path-coupled single-loop delta-sigma modulator using noise-shaped integrating quantizer," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 4005-4008, May 2010.
       
    89. B. Hershberg, S. Weaver, and U. Moon, "A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using 300mV output swing opamp," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 302-303, Feb. 2010.
       
    90. S. Weaver, B. Hershberg, P. Hanumolu, and U. Moon, "A multiplexer-based digital passive linear counter (PLINCO)," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 607-610, Dec. 2009 (Best Paper Award).
       
    91. S. Kwon, P. Hanumolu, S. Kim, S. Lee, S. You, H. Park, J. Kim, and U. Moon, "An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT delta-sigma ADC with relaxed DEM timing," IEEE Custom Int. Circuits Conf. (CICC), pp. 171-174, Sep. 2009.
       
    92. D. Gubbins, S. Kwon, B. Lee, P. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC with inherent anti-alias filtering," IEEE Custom Int. Circuits Conf. (CICC), pp. 275-278, Sep. 2009.
       
    93. T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon, "A 630uW zero-crossing-based delta-sigma ADC using switched-resistor current sources in 45nm CMOS," IEEE Custom Int. Circuits Conf. (CICC), pp. 1-4, Sep. 2009.
       
    94. O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu, and U. Moon, "A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC," IEEE Symp. VLSI Circuits (VLSI), pp. 74-75, Jun. 2009.
       
    95. M. Kim, V. Kratyuk, P. Hanumolu, G. Ahn, S. Kwon, and U. Moon, "An 8mW 10b 50MS/s pipelined ADC using 25dB opamp," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 49-52, Nov. 2008.
       
    96. S. Weaver, B. Hershberg, D. Knierim, and U. Moon, "A 6b stochastic flash analog-to-digital converter without calibration or reference ladder," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 373-376, Nov. 2008.
       
    97. D. Gubbins, B. Lee, P. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC," IEEE Custom Int. Circuits Conf. (CICC), pp. 21-24, Sep. 2008.
       
    98. I. Vytyaz, J. Carnes, T. Wu, P. Hanumolu, U. Moon, and K. Mayaram, "Noise tolerant oscillator design using perturbation projection vector analysis," IEEE Custom Int. Circuits Conf. (CICC), pp. 695-698, Sep. 2008.
       
    99. P. Kurahashi, P. Hanumolu, and U. Moon, "A 1V downconversion filter using duty-cycle controlled bandwidth tuning," IEEE Custom Int. Circuits Conf. (CICC), pp. 707-710, Sep. 2008.
       
    100. N. Maghari, S. Kwon, and U. Moon, "74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain," IEEE Custom Int. Circuits Conf. (CICC), pp. 101-104, Sep. 2008.
       
    101. J. Jaussi, G. Balamurugan, J. Kennedy, F. O'Mahony, M. Mansuri, R. Mooney, B. Casper, and U. Moon, "In-situ jitter tolerance measurement technique for serial I/O," IEEE Symp. VLSI Circuits (VLSI), pp. 168-169, Jun. 2008.
       
    102. O. Rajaee and U. Moon, "Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1212-1215, May 2008.
       
    103. I. Vytyaz, D. Lee, U. Moon, and K. Mayaram, "Parameter variation analysis for voltage controlled oscillators in phase-locked loops," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 716-719, May 2008.
       
    104. N. Maghari and U. Moon, "Multi-loop efficient sturdy MASH delta-sigma modulators," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1216-1219, May 2008.
       
    105. B.R. Gregoire and U. Moon, "Reducing the effects of component mismatch by using relative size information," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 512-515, May 2008.
       
    106. I. Vytyaz, P. Hanumolu, U. Moon, and K. Mayaram, "Periodic steady-state analysis augmented with design equality constraints," Design Auto. Test Europe (DATE), pp. 312-317, Mar. 2008.
       
    107. B.R. Gregoire and U. Moon, "An over-60dB true rail-to-rail performance using correlated level shifting and an opamp with 30dB loop gain," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 540-541, Feb. 2008.
       
    108. O. Rajaee, N. Maghari, and U. Moon, "Time-shifted CDS enhancement of comparator-based MDAC for pipelined ADC applications," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 210-213, Dec. 2007.
       
    109. J. Carnes, I. Vytyaz, P. Hanumolu, K. Mayaram, and U. Moon, "Design and analysis of noise tolerant ring oscillators using Maneatis delay cells," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 494-497, Dec. 2007.
       
    110. S. Weaver, D. Knierim, and U. Moon, "Design considerations for stochastic analog-to-digital conversion," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 234-237, Dec. 2007.
       
    111. R. Desikachari, M. Steeds, J. Huard, and U. Moon, "An efficient design procedure for high-speed low-power dual-modulus prescalers," IEEE Int. Conf. Elec. Circuits Syst. (ICECS), pp. 645-648, Dec. 2007.
       
    112. I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram, "Sensitivity analysis for oscillators," Int. Conf. Computer-Aided Design (ICCAD), pp. 458-463, Nov. 2007.
       
    113. J. Carnes, G. Ahn, and U. Moon, "A 1V 10b 60MS/s hybrid opamp-reset/switched-RC pipelined ADC," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 236-239, Nov. 2007.
       
    114. N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, "A 1.8V 36mW 11bit 80MS/s pipelined ADC using capacitor and opamp sharing," IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 240-243, Nov. 2007.
       
    115. Y. Kook, J. Li, B. Lee, and U. Moon, "Low-power and high-speed pipelined ADC using time-aligned CDS technique," IEEE Custom Int. Circuits Conf. (CICC), pp. 321-324, Sep. 2007.
       
    116. G. Ahn, M. Kim, P. Hanumolu, and U. Moon, "A 1V 10b 30MSPS switched-RC pipelined ADC," IEEE Custom Int. Circuits Conf. (CICC), pp. 325-328, Sep. 2007.
       
    117. M. Brownlee, P. Hanumolu, and U. Moon, "A 3.2Gb/s oversampling CDR with improved jitter tolerance," IEEE Custom Int. Circuits Conf. (CICC), pp. 353-356, Sep. 2007.
       
    118. V. Kratyuk, P. Hanumolu, K. Mayaram, and U. Moon, "A 0.6GHz to 2GHz digital PLL with wide tracking range," IEEE Custom Int. Circuits Conf. (CICC), pp. 305-308, Sep. 2007.
       
    119. P. Hanumolu, G. Wei, U. Moon, and K. Mayaram, "Digitally-enhanced phase-locking circuits," IEEE Custom Int. Circuits Conf. (CICC), pp. 361-368, Sep. 2007.
       
    120. T. Wu, P. Hanumolu, K. Mayaram, and U. Moon, "A 4.2 GHz PLL frequency synthesizer with an adaptively tuned coarse loop," IEEE Custom Int. Circuits Conf. (CICC), pp. 547-550, Sep. 2007.
       
    121. V. Sharma, U. Moon, and G. Temes, "Efficient pipelined ADCs using integer gain MDACs," IEEE PRIME, pp. 1-4, Jul. 2007.
       
    122. I. Vytyaz, D. Lee, S. Lu, A. Mehrotra, U. Moon, and K. Mayaram, "Parameter finding methods for oscillators withba specified oscillation frequency," Design Automation Conference (DAC), pp. 424-429, Jun. 2007.
       
    123. S. Kwon and U. Moon, "A high-speed delta-sigma modulator with relaxed DEM timing requirement," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 733-736, May 2007.
       
    124. B.R. Gregoire and U. Moon, "Process-independent resistor temperature-coefficients using series/parallel and parallel/series composite resistors," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2826-2829, May 2007.
       
    125. N. Maghari, S. Kwon, G. Temes, and U. Moon, "Mixed-order sturdy MASH delta-sigma modulator," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 257-260, May 2007.
       
    126. I. Vytyaz, D. Lee, A. Mehrotra, U. Moon, and K. Mayaram, "Periodic steady-state analysis of oscillators with a specified oscillation frequency," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1073-1076, May 2007.
       
    127. P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon, "A 0.6V highly linear Switched-R-MOSFET-C filter," IEEE Custom Int. Circuits Conf. (CICC), pp. 833-836, Sep. 2006 (Best Student Paper Award).
       
    128. P. Hanumolu, M. Kim, G. Wei, and U. Moon, "A 1.6Gbps digital clock and data recovery circuit," IEEE Custom Int. Circuits Conf. (CICC), pp. 603-606, Sep. 2006.
       
    129. V. Kratyuk, P. Hanumolu, K. Ok, K. Mayaram, and U. Moon, "A digital PLL with a stochastic time-to-digital converter," IEEE Symp. VLSI Circuits (VLSI), pp. 38-39, Jun. 2006.
       
    130. T. Wu, K. Mayaram, and U. Moon, "An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators," IEEE Symp. VLSI Circuits (VLSI), pp. 128-129, Jun. 2006.
       
    131. P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon, "A sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter," IEEE Symp. VLSI Circuits (VLSI), pp. 92-93, Jun. 2006.
       
    132. Q. Meng, K. Lee, T. Sugimoto, K. Hamashita, K. Takasuka, S. Takeuchi, U. Moon, and G. Temes, "A 0.8V 88dB dual-channel audio delta-sigma DAC with headphone driver," IEEE Symp. VLSI Circuits (VLSI), pp. 66-67, Jun. 2006.
       
    133. P. Hanumolu, G. Wei, and U. Moon, "A wide tracking range 0.2-4Gbps clock and data recovery circuit," IEEE Symp. VLSI Circuits (VLSI), pp. 88-89, Jun. 2006.
       
    134. G. Ahn, P. Hanumolu, M. Kim, S. Takeuchi1, T. Sugimoto1, K. Hamashita1, K. Takasuka1, G. Temes, and U. Moon, "A 12b 10MS/s pipelined ADC using reference scaling," IEEE Symp. VLSI Circuits (VLSI), pp. 272-273, Jun. 2006.
       
    135. M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, "A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC," IEEE Symp. VLSI Circuits (VLSI), pp. 200-201, Jun. 2006.
       
    136. M. Kim, P. Hanumolu, and U. Moon, "A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking," IEEE Symp. VLSI Circuits (VLSI), pp. 60-61, Jun. 2006.
       
    137. J. Carnes and U. Moon, "The effect of switch resistance on pipelined ADC MDAC settling time," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 5251-5254, May 2006.
       
    138. T. Wu, U. Moon, and K. Mayaram, "Dependence of LC VCO oscillation frequency on bias current," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 5039-5042, May 2006.
       
    139. N. Talebbeydokhti, P Hanumolu, P. Kurahashi, and U. Moon, "Constant transconductance bias circuit with an on-chip resistor," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2857-2860, May 2006.
       
    140. M. Brownlee, P. Hanumolu, K. Mayaram, and U. Moon, "A 0.5 to 2.5GHz PLL with fully differential supply-regulated tuning," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 588-589, Feb. 2006.
       
    141. A. Nemmani, M. Vandepas, K. Ok, K. Mayaram, and U. Moon, "Design techniques for radiation hardened phase locked loops," Mil. Aero. Prog. Logic Dev. Int. Conf. (MAPLD), Sep. 2005.
       
    142. M. Vandepas, K. Ok, A. Nemmani, M. Brownlee, K. Mayaram, and U. Moon, "Characterization of 1.2GHz phase locked loops and voltage controlled oscillators in a total dose radiation environment," Mil. Aero. Prog. Logic Dev. Int. Conf. (MAPLD), Sep. 2005.
       
    143. V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram, "A low spur fractional-N frequency synthesizer architecture," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2807-2810, May 2005.
       
    144. T. Wu, P. Hanumolu, U. Moon, and K. Mayaram, "An FMDLL based dual-loop frequency synthesizer for 5GHz WLAN applications," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 3986-3989, May 2005.
       
    145. V. Kratyuk, I. Vytyaz, U. Moon, and K. Mayaram, "Analysis of supply and ground noise sensitivity in ring and LC oscillators," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 5986-5989, May 2005.
       
    146. V. Sharma, U. Moon, and G. Temes, "A generic multilevel multiplying D/A converter for pipelined ADCs," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 6182-6185, May 2005.
       
    147. T. Rengachari, V. Sharma, G. Temes, and U. Moon, "A 10-bit algorithmic A/D converter for Cytosensor Application," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 6186-6189, May 2005.
       
    148. G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita, K. Takasuka, G. Temes, and U. Moon, "A 0.6V 82dB delta-sigma audio ADC using switched-RC integrators," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 166-167, Feb. 2005.
       
    149. X. Wang, Y. Guo, U. Moon, and G. Temes, "Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs," IEEE Custom Int. Circuits Conf. (CICC), pp. 523-526, Oct. 2004.
       
    150. G. Vemulapalli, P. Hanumolu, and U. Moon, "A 0.8V accurately-tuned continuous-time filter," IEEE Custom Int. Circuits Conf. (CICC), pp. 45-48, Oct. 2004.
       
    151. C. Myers, J. Li, D. Chang, and U. Moon, "Low voltage high-SNR pipeline data converters," IEEE Northeast Workshop Circuits Syst. (NEWCAS), pp. 245-248, Jun. 2004.
       
    152. M. Brownlee, P. Hanumolu, U. Moon, and K. Mayaram, "The effect of power supply noise on ring oscillator phase noise," IEEE Northeast Workshop Circuits Syst. (NEWCAS), pp. 225-228, Jun. 2004.
       
    153. J. Li, G. Ahn, D. Chang, and U. Moon, "0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR," IEEE Symp. VLSI Circuits (VLSI), pp. 436-439, Jun. 2004.
       
    154. P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon, "Jitter in high-speed serial and parallel links," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. IV, pp. 425-428, May 2004.
       
    155. S. Xiao, J. Silva, U. Moon, and G. Temes, "A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 433-436, May 2004.
       
    156. J. Silva, U. Moon, and G. Temes, "Low-distortion delta-sigma topologies for MASH architectures," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 1144-1147, May 2004.
       
    157. M. Kim, G. Ahn, and U. Moon, "An improved algorithmic ADC clocking scheme," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 589-592, May 2004.
       
    158. J. Li and U. Moon, "A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique," IEEE Custom Int. Circuits Conf. (CICC), pp. 413-416, Sep. 2003.
       
    159. B. Greenley, R. Veith, D. Chang, and U. Moon, "A 1.4V 10b CMOS DC DAC in 0.01mm2," IEEE Int. SOC Conf., pp. 237-238, Sep. 2003.
       
    160. M. Keskin, U. Moon, and G. Temes, "A 0.9-V 10.7-MHz 3.6-mW bandpass modulator using unity-gain-reset opamps," IEEE Int. Workshop ADC Mod. Test., pp. 63-66, Sep. 2003.
       
    161. M. Keskin, U. Moon, and G. Temes, "Amplifier imperfection effects in switched-capacitor resonators," IEEE Int. Workshop ADC Mod. Test., pp. 67-70, Sep. 2003.
       
    162. D. Chang and U. Moon, "A 0.9V 9mW 1MSPS digitally calibrated ADC with 75dB SFDR," IEEE Symp. VLSI Circuits (VLSI), pp. 67-70, Jun. 2003.
       
    163. J. Li and U. Moon, "An extended radix-based digital calibration technique for multi-stage ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 829-832, May 2003.
       
    164. A. Pulincherry, M. Hufford, E. Naviasky, and U. Moon, "Continuous-time frequency translating bandpass delta-sigma modulator," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 1013-1016, May 2003.
       
    165. D. Bruneau, A. Early, U. Moon, and G. Temes, "High-speed switched-capacitor filters based on unity gain buffer," IEEJ Int. Analog VLSI Workshop, pp. 5-9, Sep. 2002.
       
    166. M. Coe and U. Moon, "Mismatch-shaping successive-approximation ADC," IEEJ Int. Analog VLSI Workshop, pp. 60-64, Sep. 2002.
       
    167. A. Rao, W. McIntyre, U. Moon, and G. Temes, "A noise-shaped switched-capacitor DC-DC voltage regulator," IEEE European Solid-State Circuits Conf. (ESSCIRC), pp. 375-378, Sep. 2002.
       
    168. X. Wang, P. Kiss, U. Moon, and G. Temes, "Digital correlation technique for the estimation and correction of DAC errors in multibit MASH delta-sigma ADCs," Int. Conf. Advanced A/D D/A Conv. Tech. (ADDA), pp. 39-42, Jun. 2002.
       
    169. M. Keskin, M. Brown, U. Moon, and G. Temes, "A voltage-mode switched-capacitor bandpass delta-sigma modulator," Int. Conf. Advanced A/D D/A Conv. Tech. (ADDA), pp. 19-22 , Jun. 2002.
       
    170. J. Li and U. Moon, "High-speed pipelined A/D converter using time-shifted CDS technique," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 909-912, May 2002.
       
    171. A. Rao, W. McIntyre, J. Parry, U. Moon, and G. Temes, "Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. IV, pp. 743-746, May 2002.
       
    172. D. Chang and U. Moon, "Radix-based digital calibration technique for multi-stage ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. II, pp. 796-799, May 2002.
       
    173. X. Wang, U. Moon, M. Liu, and G. Temes, "Digital correlation technique for the estimation and correction of DAC errors in multibit MASH delta-sigma ADCs," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. IV, pp. 691-694, May 2002.
       
    174. D. Chang, L. Wu, and U. Moon, "Low-voltage pipelined ADC using opamp-reset switching technique," IEEE Custom Int. Circuits Conf. (CICC), pp. 461-464, May 2002.
       
    175. S. Yoo, T. Oh, J. Moon, S. Lee, and U. Moon, "A 2.5V 10b 120MSamples/s CMOS pipelined ADC with high SFDR," IEEE Custom Int. Circuits Conf. (CICC), pp. 441-444, May 2002.
       
    176. J. Sonntag, J. Stonick, J. Gorecki, B. Beale, B. Check, X. Gong, J. Guiliano, K. Lee, B. Lefferts, D. Martin, U. Moon, A. Sengir, S. Titus, G. Wei, D. Weinlader, and Y. Yang, "An adaptive PAM-4 5Gb/s backplane transceiver in 0.25um CMOS," IEEE Custom Int. Circuits Conf. (CICC), pp. 363-366, May 2002.
       
    177. J. Silva, X. Wang, P. Kiss, U. Moon, and G. Temes, "Digital techniques for improved delta-sigma data conversion," invited tutorial, IEEE Custom Int. Circuits Conf. (CICC), pp. 183-190, May 2002.
       
    178. M. Keskin, U. Moon, and G. Temes, "A 1-V 10-MHz clock-rate 13-bit CMOS delta-sigma modulator using unity-gain-reset opamps," IEEE European Solid-State Circuits Conf. (ESSCIRC), pp. 532-535, Sep. 2001.
       
    179. B. Greenley, R. Veith, and U. Moon, "A 1.8V CMOS DAC cell with ultra high gain op-amp in 0.0143mm2," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 412-415, May 2001.
       
    180. R. Perigny, U. Moon, and G. Temes "Area efficient CMOS charge pump circuits," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 492-495, May 2001.
       
    181. M. Keskin, U. Moon, and G. Temes, "Low-voltage low-sensitivity switched-capacitor bandpass delta-sigma modulator," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 348-351, May 2001.
       
    182. P. Kiss, U. Moon, J. Steensgaard, J. Stonick, and G. Temes, "Multibit delta-sigma ADC with mixed-mode DAC error correction," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 280-283, May 2001.
       
    183. T. Kajita, U. Moon, and G. Temes, "A noise-shaping accelerometer interface circuit for two-chip implementation," IEEE Inst. Meas. Techology Conf., pp. 1581-1586, May 2001.
       
    184. M. Keskin, U. Moon, and G. Temes, "Low-voltage switched-capacitor resonators," IEEE Dallas CAS Workshop Low Power Voltage Circuits Syst., pp. 19-22, March 2001.
       
    185. Z. Zheng, B. Min, U. Moon, and G. Temes, "Efficient error-cancelling algorithmic ADC," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 451-454, May 2000.
       
    186. L. Wu, M. Keskin, U. Moon, and G. Temes, " Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. V, pp. 445-448, May 2000.
       
    187. U. Moon, J. Silva, J. Steensgaard, and G. Temes, "A switched-capacitor DAC with analog mismatch correction," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. IV, pp. 421-424, May 2000.
       
    188. T. Kajita, U. Moon, and G. Temes, "A noise-shaping accelerometer interface circuit for two-chip implementation," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. IV, pp. 337-340, May 2000.
       
    189. P. Kiss, J. Silva, U. Moon, J. Stonick, and G. Temes, "Improved adaptive digital compensation for cascaded delta-sigma ADCs," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. II, pp. 33-36, May 2000.
       
    190. M. Lehne, J. Stonick, and U. Moon, "An adaptive offset cancellation mixer for direct conversion receivers in 2.4GHz CMOS," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. I, pp. 319-322, May 2000.
       
    191. U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard, and F. Maloberti, "Switched-capacitor circuit techniques in submicron low-voltage CMOS," IEEE Int. Conf. VLSI CAD, pp. 349-358, Oct. 1999.
       
    192. G. Temes, U. Moon, and J. Steensgaard, "Analog (s)witchcraft, or how to perform accurate and linear data conversion using inaccurate nonlinear elements," IEEE Elec. Circuits Syst. Conf., pp. 97-101, Sep. 1999.
       
    193. J. Steensgaard, U. Moon, and G. Temes, "Mismatch-shaping serial digital-to-analog converter," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. II, pp. 5-8, May 1999.
       
    194. Z. Zheng, U. Moon, J. Steensgaard, B. Wang, and G. Temes, "Capacitor mismatch error cancellation technique for a successive-approximation A/D converter," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. II, pp. 326-329, May 1999.
       
    195. E. Bidari, M. Keskin, F. Maloberti, U. Moon, J. Steensgaard, and G. Temes, "Low-voltage switched-capacitor circuits," IEEE Int. Symp. Circuits Syst. (ISCAS), vol. II, pp. 49-52, May 1999.
       
    196. J. Steensgaard, U. Moon, and G. Temes, "Mismatch-shaped pseudo-passive two-capacitor DAC," IEEE Alessandro Volta Workshop on Low-Power Design, pp. 144-152, March 4, 1999.
       
    197. U. Moon, A. Mastrocola, J. Alsayegh, and S. Werner, "Timing recovery in CMOS using nonlinear spectral-line method," IEEE Custom Int. Circuits Conf. (CICC), pp. 13-16, May 1996.
       
    198. R. Shariadoust, K. Lakshmikumar, U. Moon, H.S. Fetterman, M. Sankaran, D. Sherry, J. Kumar, and S. Daubert, "A high-speed, high-resolution analog front end for digital subscriber line applications," IEEE Custom Int. Circuits Conf. (CICC), pp. 289-292, May 1995.
       
    199. U. Moon and B. Song, "Low-distortion continuous-time R-MOSFET-C filters," IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1168-1171, May 1993.
       
    200. U. Moon and B. Song, "A low-distortion 22kHz 5th-order Bessel filter," IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 110-111, Feb. 1993.

     

    Graduate Thesis    Journal Papers    Conference Papers    Miscellaneous
     

    1. Hang Hu, "High-performance ring amplifier based analog-to-digital converters," Ph.D. Dissertation, Oregon State University, 2022
       
    2. Vladimir Vesely, "PLL-SAR: A new time-domain analog-to-digital converter topology," M.S. Thesis, Oregon State University, 2022.
       
    3. Calvin Lee, "Single-ended techniques for delta-sigma modulators," Ph.D. Dissertation, Oregon State University, 2021
       
    4. Lukang Shi, "Active noise shaping analog-to-digital data converters," Ph.D. Dissertation, Oregon State University, 2019
       
    5. Praveen Venkatachala, "Design considerations and circuit techniques for robust ringamps," Ph.D. Dissertation, Oregon State University, 2019
       
    6. Ahmed ElShater, "Ring amplifier optimized for high resolution analog-to-digital converter applications," Ph.D. Dissertation, Oregon State University, 2019
       
    7. Bohui Xiao, "A 1V 40mA fast transient capless LDO with 7uA quiescent current in 180nm CMOS using ring amplifier with adaptive damping," M.S. Thesis, Oregon State University, 2018.
       
    8. Michael Oatman, "An incremental ADC using passive integrators and dynamic power scaling technique," M.S. Thesis, Oregon State University, 2018.
       
    9. Spencer Leuenberger, "Ring amplifier design techniques for high-precision and high-speed amplification," Ph.D. Dissertation, Oregon State University, 2017.
       
    10. Jason Muhlestein, "Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques," Ph.D. Dissertation, Oregon State University, 2017.
       
    11. Yang Xu, "Power-efficient design techniques and architectures for scalable submicron analog circuits," Ph.D. Dissertation, Oregon State University, 2017.
       
    12. Hyuk Sun, "A wide modulation range and PVT-tolerant spread-spectrum modulation clock generator," Ph.D. Dissertation, Oregon State University, 2016.
       
    13. Allen Waters, "Automated Verilog-to-layout synthesis of ADCs using custom analog cells," Ph.D. Dissertation, Oregon State University, 2015.
       
    14. Brandilyn Coker, "Limitations and optimization of a blind calibration algorithm for nonlinearity in analog to digital converters," M.S. Thesis, Oregon State University, 2015.
       
    15. Farshad Farahbakhshian, "Dynamic biasing for ring amplification," M.S. Thesis, Oregon State University, 2014.
       
    16. Jerry Leung, "Data driven optimization in SAR ADC," M.S. Thesis, Oregon State University, 2014.
       
    17. Yue Hu, "Efficient use of time information in analog-to-digital converters," Ph.D. Dissertation, Oregon State University, 2014.
       
    18. Taehwan Oh, "Power efficient analog-to-digital converters using both voltage and time domain information," Ph.D. Dissertation, Oregon State University, 2013.
       
    19. Hariprasath Venkatram, "Energy and area efficient techniques for data converters," Ph.D. Dissertation, Oregon State University, 2013.
       
    20. Manideep Gande, "Design techniques for time based data converters," Ph.D. Dissertation, Oregon State University, 2013.
       
    21. Jon Guerber, "Time and statistical information utilization in high efficiency sub‐micron CMOS successive approximation analog to digital converters," Ph.D. Dissertation, Oregon State University, 2012.
       
    22. Ben Hershberg "Ring amplification for switched capacitor circuits," Ph.D. Dissertation, Oregon State University, 2012.
       
    23. Ho-Young Lee "Power-efficient two-step pipelined analog-to-digital conversion," Ph.D. Dissertation, Oregon State University, 2011.
       
    24. Omid Rajaee, "Design of low OSR, high precision analog-to-digital converters," Ph.D. Dissertation, Oregon State University, 2010.
       
    25. Skyler Weaver, "Automated synthesis of analog to digital conversion," Ph.D. Dissertation, Oregon State University, 2010.
       
    26. Tawfiq Musah, "Low power design techniques for analog-to-digital converters in submicron CMOS," Ph.D. Dissertation, Oregon State University, 2010.
       
    27. Nima Maghari, "Architectural compensation techniques for analog inaccuracies in delta-sigma analog-to-digital converters," Ph.D. Dissertation, Oregon State University, 2010.
       
    28. Peter Kurahashi, "Duty-cycle controlled switched resistor techniques for continuously tunable, low-voltage circuits," Ph.D. Dissertation, Oregon State University, 2009.
       
    29. Sunwoo Kwon, "A multi-bit hybrid DSM over full-scale range without feedback DEM," Ph.D. Dissertation, Oregon State University, 2009.
       
    30. Naga Sasidhar Lingam, "Low power design techniques for high speed pipelined ADCs," Ph.D. Dissertation, Oregon State University, 2009.
       
    31. Rob Gregoire, "Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps," Ph.D. Dissertation, Oregon State University, 2008.
       
    32. David Gubbins, "Continuous time input pipeline ADCs," Ph.D. Dissertation, Oregon State University, 2008.
       
    33. Igor Vytyaz, "Automated analysis, design, and optimization of low noise oscillators," Ph.D. Dissertation, Oregon State University, 2008.
       
    34. Aaron Caffee, (Reference-less linear oscillators), M.S. Project, Oregon State University, 2007.
       
    35. Xueqiang Ding, (Frequency synthesizers for communication applications), M.S. Project, Oregon State University, 2007.
       
    36. Joshua Carnes, "Low voltage techniques for pipelined analog-to-digital converters," M.S. Thesis, Oregon State University, 2007.
       
    37. Ting Wu, "Design techniques for PVT tolerant phase-locked loops," Ph.D. Dissertation, Oregon State University, 2007.
       
    38. Volodymyr Kratyuk, "Digital PLLs for multi-GHz clock generation," Ph.D. Dissertation, Oregon State University, 2006.
       
    39. Merrick Brownlee, "Low noise clocking for high speed serial links," Ph.D. Dissertation, Oregon State University, 2006.
       
    40. Pavan Hanumolu, "Design techniques for clocking high performance signaling systems," Ph.D. Dissertation, Oregon State University, 2006.
       
    41. Erik Geissenhainer, "Characterization of a digital phase locked loop and a stochastic time to digital converter," M.S. Thesis, Oregon State University, 2006.
       
    42. Mingyu Kim, "Low-power design technicuqes for low-voltage analog-to-digital converters," Ph.D. Dissertation, Oregon State University, 2006.
       
    43. Yue Zhang, (Continuous-time delta-sigma modulator), M.S. Project, Oregon State University, 2005.
       
    44. Matthew Brown, "Noise optimization of low-voltage CMOS audio preamplifier systems," M.S. Thesis, Oregon State University, 2005.
       
    45. Gil-Cho Ahn, "Design techniques for low-voltage and low-power analog-to-digital converters," Ph.D. Dissertation, Oregon State University, 2005.
       
    46. Kerem Ok, "A stochastic time-to-digital converter for digital phase-locked loops," M.S. Thesis, Oregon State University, 2005.
       
    47. Martin Vandepas, "Oscillators and phase locked loops for space radiation environments," M.S. Thesis, Oregon State University, 2005.
       
    48. Anantha Nag Nemmani, "Design techniques for radiation hardened phase-locked loops," M.S. Thesis, Oregon State University, 2005.
       
    49. Jacob Zechmann, "Investigation of a noise-shaping accelerometer interface circuit for two-chip implementation," M.S. Thesis, Oregon State University, 2005.
       
    50. Charlie Myers, "Design of high-performance pipeline analog-to-digital converters in low-voltage processes," M.S. Thesis, Oregon State University, 2005.
       
    51. John Bennett, (Implications of jitter on high speed serial interface), M.S. Project, Oregon State University, 2004.
       
    52. Jose Silva, "High-performance delta-sigma analog-to-digital data converters," Ph.D. Dissertation, Oregon State University, 2004.
       
    53. Vivek Sharma, "Generalized radix design techniques for low-power, low-voltage pipelined & cyclic analog-digital converters," M.S. Thesis, Oregon State University, 2004.
       
    54. Yuhua Guo, "A study of basic building blocks of analog-to-digital delta-sigma modulators," M.S. Thesis, Oregon State University, 2004.
       
    55. Thirumalai Rengachari, "A 10 bit algorithmic A/D converter for a biosensor," M.S. Thesis, Oregon State University, 2004.
       
    56. Shelly Xiao, "A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications," M.S. Thesis, Oregon State University, 2004.
       
    57. David Stoops, (Simulating switched capacitor circuits with SpectreRF), M.S. Project, Oregon State University, 2003.
       
    58. Kiseok Yoo, "Op-amp-free SC biquad LPF and delta-sigma ADC," M.S. Thesis, Oregon State University, 2003.
       
    59. Xuesheng Wang, "A fully digital technique for the estimation and correction of the DAC error in multi-bit delta-sigma ADCs," Ph.D. Dissertation, Oregon State University, 2003.
       
    60. Gowtham Vemulapalli, "Accurately tunable low-voltage continuous-time filter," M.S. Thesis, Oregon State University, 2003.
       
    61. Jipeng Li, "Accuracy enhancement techniques in low-voltage high-speed pipelined ADC design," Ph.D. Dissertation, Oregon State University, 2003.
       
    62. Eashwar Thiagarajan, (Low voltage filter), M.S. Project, Oregon State University, 2003.
       
    63. Ranganathan Desikachari, "High-speed CMOS dual-modulus prescalers for frequency synthesis," M.S. Thesis, Oregon State University, 2003.
       
    64. Eric Wyers, (LC oscillator), M.S. Project, Oregon State University, 2003.
       
    65. Mingliang Liu, (Oversampling data converter), M.S. Project, Oregon State University, 2003.
       
    66. Mengzhe Ma, "Design of high efficiency step-down switched-capacitor DC/DC converter," M.S. Thesis, Oregon State University, 2003.
       
    67. Anurag Pulincherry, "A continuous time frequency translating delta sigma modulator," M.S. Thesis, Oregon State University, 2002.
       
    68. Dongyoung Chang, "Design techniques for low-voltage analog-to-digital converter," Ph.D. Dissertation, Oregon State University, 2002.
       
    69. Charlie Yun, "20-stage pipelined ADC with radix-based calibration," M.S. Thesis, Oregon State University, 2002.
       
    70. Vinay Ramyead, (CMOS prescaler), M.S. Project, Oregon State University, 2002.
       
    71. Arun Rao, "An efficient switched capacitor buck-boost voltage regulator using delta-sigma control loop," M.S. Thesis, Oregon State University, 2002.
       
    72. David Bruneau, "High-speed switched-capacitor filters based on unity-gain buffers," M.S. Thesis, Oregon State University, 2002.
       
    73. Matthew Coe, "Digital implementation of a mismatch-shaping successive-approximation ADC," M.S. Thesis, Oregon State University, 2001.
       
    74. Daniel Thomas "Fast opamp-free delta sigma modulator," M.S. Thesis, Oregon State University, 2001.
       
    75. Mustafa Keskin, "Low voltage switched capacitor circuits for lowpass and bandpass converters," Ph.D. Dissertation, Oregon State University, 2001.
       
    76. Brandon Greenley, "Area efficient D/A converter for accurate DC operation," M.S. Thesis, Oregon State University, 2001.
       
    77. Ryan Perigny, "Area efficiency improvement of CMOS charge pump circuits," M.S. Thesis, Oregon State University, 2000.
       
    78. Jianping Wen, "Error canceling low-voltage SAR ADC," M.S. Thesis, Oregon State University, 2000.
       
    79. Lei Wu, "Low-voltage pipeline A/D converter," M.S. Thesis, Oregon State University, 1999.
       
    80. Zhiliang Zheng, "Low power high resolution data converter in digital CMOS technology," M.S. Thesis, Oregon State University, 1999.
       
    81. Emad Bidari, "Low-voltage switched-capacitor circuits," M.S. Thesis, Oregon State University, 1998.
       
    82. Un-Ku Moon, "Linearity improvement technique for CMOS continuous-time filters," Ph.D. Dissertation, University of Illinois, Urbana-Champaign, 1994.

     

    Miscellaneous    Journal Papers    Conference Papers    Graduate Thesis
     

    1. "OSU Wins Its First Title at SOCCER," IEEE Solid-State Circuits Magazine, vol. 11, no. 4, pp. 68-70, 2019
       
    2. "Comfortable on the Ice and in the Lab," IEEE Solid-State Circuits Magazine, vol. 11, no. 4, pp. 77-80, 2019
       
    3. "SOCCER Rematch expands field to five schools," IEEE Solid-State Circuits Magazine, vol. 6, no. 4, pp. 63-74, 2014
       
    4. "Murmann, Moon, and grad students square off at Mt. Shasta for circuits and soccer contest," IEEE Solid-State Circuits Magazine, vol. 5, no. 4, pp. 43-44, 2013
       
    5. "Shannon limit of collegiality," IEEE Solid-State Circuits Magazine, vol. 5, no. 2, pp. 14, 2013
       
    6. "SSCS-Utah chapter kickoff meeting," IEEE Solid-State Circuits Magazine, vol. 4, no. 2, pp. 72-75, 2012
       
    7. "SSCS past-president and JSSC editor-in-chief takes a hike," IEEE Solid-State Circuits Magazine, vol. 4, no. 1, pp. 57, 2012
       
    8. "DL Un-Ku Moon delivers DL talks across the United States and Canada on emerging ADCs," IEEE Solid-State Circuits Magazine, vol. 3, no. 1, pp. 75-76, 2012
       
    9. "ISSCC 2006 panel on classic circuits," IEEE Solid-State Circuits Society Newsletter, vol. 11, no. 2, pp. 11, 2006

     
Un-Ku Moon / EECS / moon@oregonstate.edu