Journal Papers
Conference Papers
Graduate Thesis
Miscellaneous

A. Waters, J. Muhlestein, and U. Moon,
"Analysis of metastability errors in conventional, LSBfirst, and
asynchronous SAR ADCs,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 63, no. 11, pp. 18981909, Nov. 2016.

Y. Xu and U. Moon,
"Chargedomain switchedgmC CBPF using semipassive chargesharing technique,"
Electron. Lett. (EL),
vol. 52, no. 20, pp. 16671669, Sep. 29, 2016.

Y. Hu, H. Venkatram, N. Maghari, and U. Moon,
"A continuoustime deltasigma ADC utilizing time information for two cycles
of excess loop delay compensation,"
IEEE Trans. Circuits Syst. II (TCAS2),
vol. 62, no. 11, pp. 10631067, Nov. 2015.

M. Gande, H. Venkatram, H. Lee, J. Guerber, and U. Moon,
"Blind calibration algorithm for nonlinearity correction based on selective
sampling,"
IEEE J. SolidState Circuits (JSSC),
vol. 49, no. 8, pp. 17151724, Aug. 2014.

T. Oh, H. Venkatram, and U. Moon,
"A timebased pipelined ADC using both voltage and time domain information,"
IEEE J. SolidState Circuits (JSSC),
vol. 49, no. 4, pp. 961971, Apr. 2014.

S. Weaver, B. Hershberg, and U. Moon,
"Digitally synthesized stochastic flash ADC using only standard digital cells,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 61, no. 1, pp. 8491, Jan. 2014.

H. Venkatram, J. Guerber, M. Gande, and U. Moon,
"Detection and correction method for single event effects in analog to
digital converters,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 60, no. 12, pp. 31633172, Dec. 2013.

T. Oh, N. Maghari, and U. Moon,
"A secondorder deltasigma ADC using noiseshaped twostep integrating
quantizer,"
IEEE J. SolidState Circuits (JSSC),
vol. 48, no. 6, pp. 14651474, Jun. 2013.

J. Guerber, H. Venkatram, M. Gande, and U. Moon,
"A ternary R2R DAC designed for improved energy efficiency,"
Electron. Lett. (EL),
vol. 49, no. 5, pp. 329330, Feb. 28, 2013.

O. Rajaee and U. Moon,
"Highly linear noiseshaped pipelined ADC utilizing a relaxed accuracy
frontend,"
IEEE J. SolidState Circuits (JSSC),
vol. 48, no. 2, pp. 502515, Feb. 2013.

B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon,
"Ring ampfliers for switched capacitor circuits,"
IEEE J. SolidState Circuits (JSSC),
vol. 47, no. 12, pp. 29282942, Dec. 2012.

J. Guerber, H. Venkatram, M. Gande, A. Waters, and U. Moon,
"A 10b ternary SAR ADC with quantization time information utilization,"
IEEE J. SolidState Circuits (JSSC),
vol. 47, no. 11, pp. 26042613, Nov. 2012.

S. Weaver, B. Hershberg, P. Hanumolu, and U. Moon,
"A multiplexerbased digital passive linear counter (PLINCO),"
Analog Int. Circuits Sig. Proc.,
vol. 73, no. 1, pp. 143149, Oct. 2012 (DOI 10.1007/s1047001298623).

N. Sasidhar, D. Gubbins, P. Hanumolu, and U. Moon,
"Railtorail input pipelined ADC incorporating multistage signal mapping,"
IEEE Trans. Circuits Syst. II (TCAS2),
vol. 59, no. 9, pp. 558562, Sep. 2012.

J. Guerber, M. Gande, and U. Moon,
"The analysis and application of redundant multistage ADC resolution
improvements through PDF residue shaping,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 59, no. 8, pp. 17331742, Aug. 2012.

N. Maghari and U. Moon,
"A thirdorder deltasigma modulator using noiseshaped bidirectional
singleslop quantizer,"
IEEE J. SolidState Circuits (JSSC),
vol. 46, no. 12, pp. 28822891, Dec. 2011.

S. Weaver, B. Hershberg, N. Maghari, and U. Moon,
"Dominologicbased ADC for digital synthesis,"
IEEE Trans. Circuits Syst. II (TCAS2),
vol. 58, no. 11, pp. 744747, Nov. 2011.

O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon,
"LowOSR overranging hybrid ADC incorporating noiseshaped twostep quantizer,"
IEEE J. SolidState Circuits (JSSC),
vol. 46, no. 11, pp. 24582468, Nov. 2011.

T. Oh, N. Maghari, D. Gubbins, and U. Moon,
"Analysis of residue integration sampling with improved jitter immunity,"
IEEE Trans. Circuits Syst. II (TCAS1),
vol. 58, no. 7, pp. 417421, Jul. 2011.

I. Vytyaz, P. Hanumolu, U. Moon, and K. Mayaram,
"Designoriented analysis of circuits with equality constraints,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 58, no. 5, pp. 10891098, May 2011.

T. Musah and U. Moon,
"Correlated level shifting integrator with reduced sensitivity to amplifier
gain,"
Electron. Lett. (EL),
vol. 47, no. 2, pp. 9192, Jan. 29, 2011.

B. Hershberg, S. Weaver, and U. Moon,
"Design of a splitCLS pipelined ADC with full signal swing using an accurate
but fractional signal swing opamp,"
IEEE J. SolidState Circuits (JSSC),
vol. 45, no. 12, pp. 26232633, Dec. 2010.

S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, and U. Moon,
"Stochastic flash analogtodigital conversion,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 57, no. 11, pp. 28252833, Nov. 2010.

D. Gubbins, B. Lee, P. Hanumolu, and U. Moon,
"Continuoustime input pipeline ADCs,"
IEEE J. SolidState Circuits (JSSC),
vol. 45, no. 8, pp. 14561468, Aug. 2010.

Y. Hu, N, Maghari, T. Musah, and U. Moon,
"Timeinterleaved noiseshaping integrating quantisers,"
Electron. Lett. (EL),
vol. 46, no. 11, pp. 757758, May 27, 2010.

H. Venkatram, J. Guerber, S. Lee, and U. Moon,
"Merged capacitor switching based SAR ADC with highest switching
energyefficiency,"
Electron. Lett. (EL),
vol. 46, no. 9, pp. 620621, Apr. 29, 2010.

O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita,
and U. Moon,
"Design of a 79dB 80MHz 8XOSR hybrid deltasigma/pipeline ADC,"
IEEE J. SolidState Circuits (JSSC),
vol. 45, no. 4, pp. 719730, Apr. 2010.

C. Peach, U. Moon, and D. Allstot,
"A 11.1mW 42MS/s 10b ADC with twostep settling in 0.18um CMOS,"
IEEE J. SolidState Circuits (JSSC),
vol. 45, no. 2, pp. 391400, Feb. 2010.

N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu,
and U. Moon,
"A low power pipelined ADC using capacitor and opamp sharing technique
with a scheme to cancel the effect of signal dependent kickback,"
IEEE J. SolidState Circuits (JSSC),
vol. 44, no. 9, pp. 23922401, Sep. 2009.

M. Kim, P. Hanumolu, and U. Moon,
"A 10MS/s 11b 0.19mm^2 algorithmic ADC with improved clocking scheme,"
IEEE J. SolidState Circuits (JSSC),
vol. 44, no. 9, pp. 23482355, Sep. 2009.

V. Kratyuk, P. Hanumolu, K. Ok, U. Moon, and K. Mayaram,
"A digital PLL with a stochastic timetodigital converter,"
IEEE Trans. Circuits Syst. I (TCAS1),
vol. 56, no. 8, pp. 16121621, Aug. 2009.

N. Maghari, S. Kwon, and U. Moon,
"74dB SNDR multiloop sturdyMASH deltasigma modulator using 35dB
openloop opamp gain,"
IEEE J. SolidState Circuits (JSSC),
vol. 44, no. 8, pp. 22122221, Aug. 2009.

T. Musah and U. Moon,
"Correlated level shifting technique with crosscoupled gainenhancement
capacitors,"
Electron. Lett. (EL),
vol. 45, no. 13, pp. 672674, Jun. 18, 2009.

N. Maghari, G. Temes, and U. Moon,
"Noiseshaped integrating quantizers in deltasigma modulators,"
Electron. Lett. (EL),
vol. 45, no. 12, pp. 612613, Jun. 4, 2009.

I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram,
"Automated design and optimization of lownoise oscillators,"
IEEE Trans. ComputerAided Design (TCAD),
pp. 609622, May 2009.

K. Lee, Q. Meng, T. Sugimoto, K. Hamashita, K. Takasuka, K. Takeuchi,
U. Moon, and G. Temes,
"A 0.8V, 2.6mW 88dB dualchannel audio deltasigma D/A converter with
headphone driver,"
IEEE J. SolidState Circuits (JSSC),
vol. 44, no. 3, pp. 916927, Mar. 2009.

T. Wu, P. Hanumolu, K. Mayaram, and U. Moon,
"Method for a constant loop bandwidth in LCVCO PLL frequency synthesizers,"
IEEE J. SolidState Circuits (JSSC),
vol. 44, no. 2, pp. 427435, Feb. 2009.

N. Maghari, G. Temes, and U. Moon,
"Singleloop deltasigma modulator with extended dynamic range,"
Electron. Lett. (EL),
vol. 44, no. 25, pp. 14521453, Dec. 4, 2008.

B.R. Gregoire and U. Moon,
"An over60dB true railtorail performance using correlated level shifting
and an opamp with only 30dB loop gain,"
IEEE J. SolidState Circuits (JSSC),
vol. 43, no. 12, pp. 26202630, Dec. 2008.

I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram,
"Sensitivity analysis for oscillators,"
IEEE Trans. ComputerAided Design (TCAD),
pp. 15211534, Sep. 2008.

M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes,
and U. Moon,
"A 0.9V 92dB doubledsampled switchedRC
deltasigma audio ADC,"
IEEE J. SolidState Circuits (JSSC),
vol. 43, no. 5, pp. 11951206, May 2008.

P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon,
"A subpicosecond resolution 0.51.5 GHz
digitaltophase converter,"
IEEE J. SolidState Circuits (JSSC),
vol. 43, no. 2, pp. 414424, Feb. 2008.

P. Hanumolu, G. Wei, and U. Moon,
"A widetracking range clock and data
recovery circuit,"
IEEE J. SolidState Circuits (JSSC),
vol. 43, no. 2, pp. 425439, Feb. 2008.

T. Musah, B.R. Gregoire, E. Naviasky, and U. Moon,
"Parallel correlated double sampling
technique for pipelined analoguetodigital converters,"
Electron. Lett. (EL),
vol. 43, no. 23, Nov. 8, 2007.

P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon,
"Design of lowvoltage highly linear
switchedRMOSFETC filters,"
IEEE J. SolidState Circuits (JSSC),
vol. 42, no. 8, pp. 16991709, Aug. 2007.

R. Wang, S. Kim, S. Lee, S. You, J. Kim, U. Moon, and G. Temes,
"A 100dB gaincorrected deltasigma
audio DAC with headphone driver,"
Analog Int. Circuits Sig. Proc.,
vol. 51, pp. 2731, Apr. 2007.

T. Wu, K. Mayaram, and U. Moon,
"An onchip calibration technique for
reducing supply voltage sensitivity in ring oscillators,"
IEEE J. SolidState Circuits (JSSC),
vol. 42, no. 4, pp. 775783, Apr. 2007.

B.R. Gregoire and U. Moon,
"A sub 1V constant GmC
switchedcapacitor current source,"
IEEE Trans. Circuits Syst. II (TCAS2),
vol. 54, no. 3, pp. 222226, Mar. 2007.

V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram,
"A design procedure for alldigital
phaselocked loops based on a chargepump phaselockedloop analogy,"
IEEE Trans. Circuits Syst. II (TCAS2),
vol. 54, no. 3, pp. 247251, Mar. 2007.

V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram,
"Frequency detector for fast frequency lock
of digital PLLs,"
Electron. Lett. (EL),
vol. 43, no. 1, pp. 1314, Jan. 4, 2007.

M. Brownlee, P. Hanumolu, K. Mayaram, U. Moon,
"A 0.5GHz to 0.5GHz PLL with fully
differential supply regulated tuning,"
IEEE J. SolidState Circuits (JSSC),
vol. 41, no. 12, pp. 27202728, Dec. 2006.

N. Maghari, S. Kwon, G. Temes, and U. Moon,
"Sturdy MASH deltasigma modulator,"
Electron. Lett. (EL),
vol. 42, no. 22, pp. 12691270, Oct. 26, 2006.

J. Li, U. Moon, J. McNeill, M. Coln, and B. Larivee,
"Comments on "Split ADC" architecture for
deterministic digital background calibration of a 16bit 1MS/s ADC,"
(correspondence letter)
IEEE J. SolidState Circuits (JSSC),
vol. 41, no. 6, pp. 1481, Jun. 2006.

G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita,
K. Takasuka, G. Temes, and U. Moon,
"A 0.6V 82dB deltasigma audio ADC using
switchedRC integrators,"
IEEE J. SolidState Circuits (JSSC),
vol. 40, no. 12, pp. 23982407, Dec. 2005.

A. Pulincherry, M. Hufford, E. Naviasky, and U. Moon,
"A timedelay jitter insensitive
continuoustime bandpass deltasigma modulator architecture,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 680684, Oct. 2005.

P. Hanumolu, G. Wei, and U. Moon,
"Equalizers for highspeed serial links,"
Int. J. High Speed Elec. Syst.,
vol. 15, no. 2, pp. 429458, Jun. 2005 (also published as a book chapter).

G. Vemulapalli, P. Hanumolu, Y. Kook, and U. Moon,
"A 0.8V, accurately tuned, linear
continuoustime filter,"
IEEE J. SolidState Circuits (JSSC),
vol. 40, no. 9, pp. 19721977, Sep. 2005.

B. Greenley, R. Veith, D. Chang, and U. Moon,
"A lowvoltage 10bit CMOS DAC in
0.01 mm^{2} die area,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 246250, May 2005.

V. Sharma, A. Narayanan, T. Rengachari, G. Temes, F. Chaplen, and U. Moon,
"A lowcost, portable generic biotoxicity
assay for environmental monitoring applications,"
Biosensors and Bioelectronics,
vol. 20/11, pp. 22182227, May 2005.

J. Li, G. Ahn, D. Chang, and U. Moon,
"A 0.9V 12mW 5MSPS algorithmic ADC with
77dB SFDR,"
IEEE J. SolidState Circuits (JSSC),
vol. 40, no. 4, pp. 960969, Apr. 2005.

A. Rao, W. McIntyre, U. Moon, and G. Temes,
"Noise shaping techniques applied to
switched capacitor voltage regulators,"
IEEE J. SolidState Circuits (JSSC),
vol. 40, no. 2, pp. 422429, Feb. 2005.

D. Chang, G. Ahn, and U. Moon,
"Sub1V design techniques for
highlinearity multistage/pipelined analogtodigital converters,"
IEEE Trans. Circuits Syst. I (TCAS1),
pp. 112, Jan. 2005.

D. Chang, J. Li, and U. Moon,
"Radixbased digital calibration
techniques for multistage recycling pipelined ADCs,"
IEEE Trans. Circuits Syst. I (TCAS1),
pp. 21332140, Nov. 2004.

P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon,
"Analysis of chargepump phasedlocked
loops,"
IEEE Trans. Circuits Syst. I (TCAS1),
pp. 16651674, Sep. 2004.

J. Li and U. Moon,
"A 1.8V 67mW 10b 100MS/s pipelined ADC
using timeshifted CDS technique,"
IEEE J. SolidState Circuits (JSSC),
vol. 39, no. 9, pp. 14681476, Sep. 2004.

S. Yoo, J. Park, S. Lee, and U. Moon,
"A 2.5V 10b 120MSample/s CMOS pipelined
ADC based on mergedcapacitor switching,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 269275, May 2004.

C. Myers, B. Greenley, D. Thomas, and U. Moon,
"Continuoustime filter design optimized
for reduced die area,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 105110, Mar. 2004.

U. Moon and G. Huang,
"CMOS implementation of nonlinear
spectralline timing recovery in digital datacommunication systems,"
IEEE Trans. Circuits Syst. I (TCAS1),
pp. 298308, Feb. 2004.

P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon,
"Analysis of PLL clock jitter in
highspeed serial links,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 879886, Nov. 2003.

J. Li and U. Moon,
"Background calibration techniques for
multistage pipelined ADCs with digital redundancy,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 531538, Sep. 2003.

D. Chang and U. Moon,
"A 1.4V 10bit 25MSPS pipelined ADC using
opampreset switching technique,"
IEEE J. SolidState Circuits (JSSC),
vol. 38, no. 8, pp. 14011404, Aug. 2003.

Y Qu, N. Barton, R. Fetche, N. Seshan, T. Fiez, U. Moon, and K. Mayaram,
"Phase noise simulation and estimation
methods: a comparative study,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 635638, Sep. 2002.

T. Kajita, U. Moon, and G. Temes,
"A twochip interface for a MEMS
accelerometer,"
IEEE Trans. Inst. Meas.,
vol. 51, no. 4, pp. 853858, Aug. 2002.

M. Keskin, U. Moon, and G. Temes,
"A 1V, 10MHz clockrate, 13bit CMOS
deltasigma modulator,"
IEEE J. SolidState Circuits (JSSC),
vol. 37, no. 7, pp. 817824, Jul. 2002.

T. Kajita, U. Moon, G. Temes,
"A noiseshaping accelerometer interface
circuit for twochip implementation,"
VLSI Design,
pp. 355361, Jun. 2002.

U. Moon, K. Mayaram, and J. Stonick,
"Spectral analysis of timedomain phase
jitter measurements,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 321327, May 2002.

M. Keskin, U. Moon, and G. Temes,
"Directchargetransfer pseudoNpath
SC circuit insensitive to the element mismatch and opamp nonidealities,"
Analog Int. Circuits Sig. Proc.,
vol. 30, pp. 243247, Mar. 2002.

J. Silva, U. Moon, J. Steensgaard, and G. Temes,
"A wideband lowdistortion deltasigma
ADC topology,"
Electron. Lett. (EL),
vol. 37, no. 12, pp. 737738, Jun. 7, 2001.

D. Chang and U. Moon,
"1V input sampling circuit with improved
linearity,"
Electron. Lett. (EL),
vol. 37, no. 8, pp. 479481, Apr. 8, 2001.

X. Wang, P. Kiss, U. Moon, J. Steensgaard, and G. Temes,
"Digital estimation and correction of
DAC errors in multibit deltasigma ADCs,"
Electron. Lett. (EL),
vol. 37, no. 7, pp. 414415, Mar. 29, 2001.

M. Keskin, U. Moon, and G. Temes,
"Switchedcapacitor resonator structure
with improved performance,"
Electron. Lett. (EL),
vol. 37, no. 4, pp. 212213, Feb. 15, 2001.

T. Kajita, G. Temes, and U. Moon,
"Correlated double sampling integrator
insensitive to parasitic capacitance,"
Electron. Lett. (EL),
vol. 37, no. 3, pp. 151153, Feb. 1, 2001.

P. Kiss, U. Moon, J. Steensgaard, J. Stonick, and G. Temes,
"Highspeed deltasigma ADC with error
correction,"
Electron. Lett. (EL),
vol. 37, no. 2, pp. 7677, Jan. 18, 2001.

W. Wilson, U. Moon, K. Lakshmikumar, and L. Dai,
"A CMOS selfcalibrating frequency
synthesizer,"
IEEE J. SolidState Circuits (JSSC),
vol. 35, no. 10, pp. 14371444, Oct. 2000.

P. Kiss, J. Silva, A. Wiesbauer, T. Sun, U. Moon, J. Stonick, and G. Temes,
"Adaptive digital correction of analog
errors in MASH ADCs  Part II. Correction using testsignal injection,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 629638, Jul. 2000.

U. Moon,
"CMOS highfrequency switchedcapacitor
filters for telecommunication applications,"
IEEE J. SolidState Circuits (JSSC),
vol. 35, no. 2, pp. 212220, Feb. 2000.

U. Moon, J. Silva, J. Steensgaard, and G. Temes,
"Switchedcapacitor DAC with analog
mismatch correction,"
Electron. Lett. (EL),
vol. 35, no. 22, pp. 19031904, Oct. 28, 1999.

U. Moon, J. Steensgaard, and G. Temes,
"Digital techniques for improving the
accuracy of data converters,"
IEEE Comm. Magazine,
pp. 136143, Oct. 1999.

J. Steensgaard, U. Moon, and G. Temes,
"Mismatchshaping switching for
twocapacitor DAC,"
Electron. Lett. (EL),
vol. 34, no. 17, pp. 16331634, Aug. 20, 1998.

U. Moon and B. Song,
"Background digital calibration techniques
for pipelined ADCs,"
IEEE Trans. Circuits Syst. II (TCAS2),
pp. 102109, Feb. 1997.

U. Moon and B. Song,
"Design of a lowdistortion 22kHz 5thorder
Bessel filter,"
IEEE J. SolidState Circuits (JSSC),
vol. 28, no. 12, pp. 12541264, Dec. 1993.
Conference Papers
Journal Papers
Graduate Thesis
Miscellaneous

T. He, M. Kareppagoudr, Y. Zhang, U. Moon, and G. Temes,
"Pseudopseudo differential circuits,"
IEEE Midwest Symp. Circuits Syst. (MWSCAS),
Aug. 2017.

J. Muhlestein, F. Farahbakhshian, P. Venkatachala, and U. Moon,
"A multipath ring amplifier with dynamic biasing,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 16211624, May 2017.

P. Venkatachala, A. ElShater, Y. Xu, M. ElChammas, and U. Moon,
"Voltage domain correction technique for timing skew errors in
time interleaved ADCs,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 14321435, May 2017.

Y. Xu, P. Venkatachala, and U. Moon,
"A highly compact wideband continuoustime transimpedance lowpass filter,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 16251628, May 2017.

J. Muhlestein, S. Leuenberger, H. Sun, Y. Xu, and U. Moon,
"A 73dB SNDR 20MS/s 1.28mW SARTDC using hybrid twostep quantization,"
IEEE Custom Int. Circuits Conf. (CICC),
May 2017.

S. Leuenberger, J. Muhlestein, H. Sun, P. Venkatachala, and U. Moon,
"A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone
ring amplifier,"
IEEE Custom Int. Circuits Conf. (CICC),
May 2017.

H. Sun, K. Sobue, K. Hamashita, T. Anand, and U. Moon,
"A 0.951 ps rms period jitter, 3.2% modulation range, DSMfree,
spreadspectrum PLL,"
IEEE Custom Int. Circuits Conf. (CICC),
May 2017.

Y. Xu, J. Muhlestein, and U. Moon,
"A 0.65mW 20MHz 5thorder lowpass filter with +28.8dBm IIP3 using
source follower coupling,"
IEEE Custom Int. Circuits Conf. (CICC),
May 2017.

C. Myers, S. Leuenberger, A. ElShater, and U. Moon,
"A design for a 6bit ENOB 20GHz input bandwidth ADC operating at 40Gs/s in
0.18um SiGe BiCMOS,"
Gov. Microcir. Apps. Critical Tech. Conf. (GOMAC),
May 2017.

H. Sun, J. Muhlestein, S. Leuenberger, K. Sobue, K. Hamashita, and U. Moon,
"A 50 MHz bandwidth 54.2 dB SNDR referencefree stochastic ADC using
VCObased quantizers,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 325328, Nov. 2016.

D. Robertson, A. Buchwald, M. Flynn, H. Lee, U. Moon, and B. Murmann,
"Data converter reflections: 19 papers from the last ten years that
deserve a second kook,"
IEEE European SolidState Circuits Conf. (ESSCIRC),
pp. 161164, Sep. 2016.

Y. Xu, S. Leuenberger, P. Venkatachala, and U. Moon,
"A 0.6mW 31MHz 4thorder lowpass filter with +29dBm IIP3 using selfcoupled
source follower based biquads in 0.18um CMOS,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 132133, Jun. 2016.

Y. Xu, P. Venkatachala, S. Leuenberger, and U. Moon,
"A 7.5mW 3570MHz 4thorder semipassive chargesharing bandpass filter with
programmable bandwidth and 72dB stopband rejection in 65nm CMOS,"
IEEE Radio Freq. Int. Circuits Symp. (RFIC),
pp. 162165, May 2016.

H. Sun, K. Sobue, K. Hamashita, and U. Moon,
"A power efficient PLL with inloopbandwidth spreadspectrum modulation using
a chargebased discretetime loop filter,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 27552758, May 2016.

H. Sun, J. Muhlestein, and U. Moon,
"A VCObased spatial averaging stochastic ADC,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 272275, Dec. 2015.

A. Waters, J. Mushlestein, and U. Moon,
"Analysis of metastability errors in asynchronous SAR ADCs,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 547550, Dec. 2015.

J. Muhlestein, H. Venkatram, J. Guerber, A. Waters, and U. Moon,
"Biterrorrate analysis and mixed signal triple modular redundancy methods
for data converters,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 421424, Dec. 2015.

A. Waters and U. Moon,
"A fully automated Verilogtolayout synthesized ADC demonstrating 56dBSNDR
with 2MHzBW,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 6972, Nov. 2015.

Y. Xu, H. Sun, and U. Moon,
"Analysis of discretetime chargedomain complex bandpass filter with
accurately tunable center frequency,"
IEEE Midwest Symp. Circuits Syst. (MWSCAS),
pp. 109112, Aug 2015.

H. Sun and U. Moon,
"MDLL/PLL dualpath clock generator,"
IEEE Midwest Symp. Circuits Syst. (MWSCAS),
pp. 197200, Aug 2015.

A. Waters and U. Moon,
"Practical modeling of comparator metastability for conventional and LSBfirst
SAR ADCs,"
IEEE Midwest Symp. Circuits Syst. (MWSCAS),
pp. 4952, Aug 2015.

Y. Xu, S. Leuenberger, and U. Moon,
"Highly linear continuoustime MASH deltasigma ADC with dual VCObased
quantizers,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 20332036, May 2015.

S. Leuenberger and U. Moon,
"A single opamp 2ndorder deltasigma ADC with a double integrating quantizer,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 309312, May 2015.

Y. Hu, S. Leuenberger, Y. Xu, and U. Moon,
"Timeinterleaved integrating quantizer incorporating channel coupling for
speed and linearity enhancement,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 22492252, May 2015.

J. Leung, A. Waters, and U. Moon,
"Selectable starting bit SAR ADC,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 16541657, May 2015.

A. Waters, J. Leung, M. Gande, and U. Moon,
"A deltasigma ADC using an LSBfirst SAR quantizer,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 16381641, May 2015.

S. Leuenberger, A. Waters, and U. Moon,
"Resistive correction of low output impedance highspeed currentsteering DACs,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 459462, Dec. 2014.

A. Waters, J. Leung, and U. Moon,
"LSBfirst SAR ADC with bitrepeating for reduced energy consumption,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 203206, Dec. 2014.

A. Waters, S. Leuenberger, and U. Moon,
"Analysis and performance tradeoffs of linearity calibration for stochastic
ADCs,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 207210, Dec. 2014.

N. Maghari and U. Moon,
"Emerging analogtodigital converters,"
IEEE European SolidState Circuits Conf. (ESSCIRC),
pp. 4350, Sep. 2014.

Y. Hu, Y. Xu, and U. Moon,
"Inherently linear time symmetric pulse width modulation,"
IEEE Custom Int. Circuits Conf. (CICC),
Sep. 2014.

H. Venkatram, T. Oh, K. Sobue, K. Hamashita, and U. Moon,
"A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using
dynamic amplifier,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 3738, Jun. 2014.

F. Farahbakhshian, A. Waters, J. Muhlestein, and U. Moon,
"Stochastic approximation register ADC,"
IEEE Northeast Workshop Circuits Syst. (NEWCAS),
pp. 189192, Jun. 2014 (Best Paper Award).

Y. Hu, F. Farahbakhshian, and U. Moon,
"Time amplifiers based on phase accumulation,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 23492352, Jun. 2014.

B. Hershberg and U. Moon,
"The ring amplifier: scalable amplification with ring oscillators,"
Workshop on Advances in Analog Circuit and Design (AACD),
Apr. 2014 (also published as a Springer book chapter).

M. Gande, H. Lee, H. Venkatram, and U. Moon,
"Blind background calibration of harmonic distortion based on selective
sampling,"
IEEE Custom Int. Circuits Conf. (CICC),
Sep. 2013.

H. Venkatram, B. Hershberg, T. Oh, M. Gande, K. Sobue, K. Hamashita,
and U. Moon,
"Parallel gain enhancement technique for switchedcapacitor circuits,"
IEEE Custom Int. Circuits Conf. (CICC),
Sep. 2013.

T. Oh, H. Venkatram, and U. Moon,
"A 70MS/s 69.3dB SNDR 38.2fJ/conversionstep timebased pipelined ADC,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 9697, Jun. 2013.

B. Hershberg and U. Moon,
"A 75.9dBSNDR 2.96mW 29fJ/convstep ringamponly pipelined ADC,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 9495, Jun. 2013.

M. Gande, J. Guerber, and U. Moon,
"Analysis of backend flash in a 1.5b/stage pipelined ADC,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 22472250, May 2013.

M. Gande, N. Maghari, T. Oh, and U. Moon,
"A 71dB dynamic rage thirdorder deltasigma TDC using chargepump,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 168169, Jun. 2012.

T. Oh, N. Maghari, and U. Moon,
"A 5MHz BW 70.7dB SNDR noiseshaped twostep quantizer based deltasigma ADC,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 162163, Jun. 2012.

B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon,
"A 61.5dB SNDR pipelined ADC using simple highlyscalable ring amplifiers,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 3233, Jun. 2012.

B. Hershberg, T. Musah, S. Weaver, and U. Moon,
"The effect of correlated level shifting on noise performance in switched
capacitor circuits,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 942945, May 2012.

H. Venkatram, T. Oh, J. Guerber, and U. Moon,
"ClassA+ amplifier with controlled positive feedback for discretetime
signal processing circuits,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 428431, May 2012.

J. Guerber, H. Venkatram, T. Oh, and U. Moon,
"Enhanced SAR ADC energy efficiency from the early reset merged capacitor
switching algorithm,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 23612364, May 2012.

T. Oh, H. Venkatram, J. Guerber, and U. Moon,
"Correlated jitter sampling for jitter cancellation in pipelined TDC,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 810813, May 2012.

B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon,
"Ring amplifier for switchedcapacitor circuits,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 460461, Feb. 2012.

H. Lee, B. Lee, and U. Moon,
"A 31.3fJ/conversionstep 70.4dB SNDR 30MS/s 1.2V twostep pipelined ADC
in 0.13um CMOS,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 474475, Feb. 2012.

J. Guerber, M. Gande, H. Venkatram, A. Waters, and U. Moon,
"A 10b ternary SAR ADC with decision time quantization based redundancy,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 6568, Nov. 2011.

B.R. Gregoire, T. Musah, N. Maghari, S. Weaver, and U. Moon,
"A 30% beyond Vdd signal swing 9ENOB pipelined ADC using a 1.2V 30dB
loopgain opamp,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 345348, Nov. 2011.

H. Lee, D. Gubbins, B. Lee, and U. Moon,
"A 0.7V 810uW 30MS/s comparatorbased twostep pipelined ADC,"
IEEE Custom Int. Circuits Conf. (CICC),
Sep. 2011.

S. Weaver, B. Hershberg, and U. Moon,
"Digitally synthesized stochastic flash ADC using only standard digital cells,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 266267, Jun. 2011.

O. Rajaee and U. Moon,
"A 12ENOB 6XOSR noiseshaped pipelined ADC utilizing a 9bit linear
frontend,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 3435, Jun. 2011.

B. Hershberg, S. Weaver, S. Takeuchi, K. Hamashita, and U. Moon,
"Binary Access Memory: An optimized lookup table for successive approximation
applications,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 16201623, May 2011.

N. Maghari and U. Moon,
"A thirdorder DT deltasigma modulator using noiseshaped bidirectional
singleslope quantizer,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 474475, Feb. 2011.

H. Venkatram, R. Inti, and U. Moon,
"Least mean square calibration method for VCO nonlinearity,"
IEEE Int. Conf. Microelec. (ICM),
pp. 14, Dec. 2010.

S. Weaver, B. Hershberg, and U. Moon,
"ENOB calculation for ADCs with inputcorrelated quantization error using a
sinewave test,"
IEEE Int. Conf. Microelec. (ICM),
pp. 58, Dec. 2010.

H. Venkatram, B. Hershberg, and U. Moon,
"Asynchronous CLS for zero crossing based circuits,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 10251028, Dec. 2010.

S. Weaver, B. Hershberg, and U. Moon,
"PDF folding for stochastic flash ADCs,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 770773, Dec. 2010.

O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon,
"A 1.2V, 78dB HDSP ADC with 3.1V input signal range,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
Nov. 2010.

N. Maghari, S. Weaver, and U. Moon,
"A +5dBFS thirdorder extended dynamic range singleloop deltasigma
modulator,"
IEEE Custom Int. Circuits Conf. (CICC),
Sep. 2010.

T. Musah and U. Moon,
"Pseudodifferential zerocrossingbased circuits with differential
error suppression,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 17311734, May 2010.

O. Rajaee, Y. Hu, M. Gande, and U. Moon,
"An interstage correlated double sampling technique for switchedcapacitor
gain stages,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 12521255, May 2010.

N. Maghari and U. Moon,
"Precise areacontrolled returntozero current steering DAC with
reduced sensitivity to clock jitter,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 297300, May 2010.

N. Maghari and U. Moon,
"A doublesampled pathcoupled singleloop deltasigma modulator using
noiseshaped integrating quantizer,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 40054008, May 2010.

B. Hershberg, S. Weaver, and U. Moon,
"A 1.4V signal swing hybrid CLSopamp/ZCBC pipelined ADC using 300mV
output swing opamp,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 302303, Feb. 2010.

S. Weaver, B. Hershberg, P. Hanumolu, and U. Moon,
"A multiplexerbased digital passive linear counter (PLINCO),"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 607610, Dec. 2009 (Best Paper Award).

S. Kwon, P. Hanumolu, S. Kim, S. Lee, S. You, H. Park, J. Kim, and U. Moon,
"An 11mW 100MHz 16XOSR 64dBSNDR hybrid CT/DT deltasigma ADC
with relaxed DEM timing,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 171174, Sep. 2009.

D. Gubbins, S. Kwon, B. Lee, P. Hanumolu, and U. Moon,
"A continuoustime input pipeline ADC with inherent antialias filtering,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 275278, Sep. 2009.

T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon,
"A 630uW zerocrossingbased deltasigma ADC using switchedresistor
current sources in 45nm CMOS,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 14, Sep. 2009.

O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu,
and U. Moon,
"A 79dB 80MHz 8XOSR hybrid deltasigma/pipeline ADC,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 7475, Jun. 2009.

M. Kim, V. Kratyuk, P. Hanumolu, G. Ahn, S. Kwon, and U. Moon,
"An 8mW 10b 50MS/s pipelined ADC using 25dB opamp,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 4952, Nov. 2008.

S. Weaver, B. Hershberg, D. Knierim, and U. Moon,
"A 6b stochastic flash analogtodigital converter without calibration
or reference ladder,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 373376, Nov. 2008.

D. Gubbins, B. Lee, P. Hanumolu, and U. Moon,
"A continuoustime input pipeline ADC,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 2124, Sep. 2008.

I. Vytyaz, J. Carnes, T. Wu, P. Hanumolu, U. Moon, and K. Mayaram,
"Noise tolerant oscillator design using perturbation projection vector
analysis,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 695698, Sep. 2008.

P. Kurahashi, P. Hanumolu, and U. Moon,
"A 1V downconversion filter using dutycycle controlled bandwidth tuning,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 707710, Sep. 2008.

N. Maghari, S. Kwon, and U. Moon,
"74dB SNDR multiloop sturdyMASH deltasigma modulator using 35dB opamp gain,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 101104, Sep. 2008.

J. Jaussi, G. Balamurugan, J. Kennedy, F. O'Mahony, M. Mansuri, R. Mooney,
B. Casper, and U. Moon,
"Insitu jitter tolerance measurement technique for serial I/O,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 168169, Jun. 2008.

O. Rajaee and U. Moon,
"Enhanced multibit deltasigma
modulator with twostep pipeline quantizer,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 12121215, May 2008.

I. Vytyaz, D. Lee, U. Moon, and K. Mayaram,
"Parameter variation analysis for voltage
controlled oscillators in phaselocked loops,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 716719, May 2008.

N. Maghari and U. Moon,
"Multiloop efficient sturdy MASH
deltasigma modulators,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 12161219, May 2008.

B.R. Gregoire and U. Moon,
"Reducing the effects of component
mismatch by using relative size information,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 512515, May 2008.

I. Vytyaz, P. Hanumolu, U. Moon, and K. Mayaram,
"Periodic steadystate analysis augmented with design equality constraints,"
Design Auto. Test Europe (DATE),
pp. 312317, Mar. 2008.

B.R. Gregoire and U. Moon,
"An over60dB true railtorail performance
using correlated level shifting and an ppamp with 30dB loop gain,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 540541, Feb. 2008.

O. Rajaee, N. Maghari, and U. Moon,
"Timeshifted CDS enhancement of comparatorbased MDAC for pipelined ADC
applications,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 210213, Dec. 2007.

J. Carnes, I. Vytyaz, P. Hanumolu, K. Mayaram, and U. Moon,
"Design and analysis of noise tolerant ring oscillators using Maneatis delay
cells,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 494497, Dec. 2007.

S. Weaver, D. Knierim, and U. Moon,
"Design considerations for stochastic analogtodigital conversion,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 234237, Dec. 2007.

R. Desikachari, M. Steeds, J. Huard, and U. Moon,
"An efficient design procedure for highspeed lowpower dualmodulus
prescalers,"
IEEE Int. Conf. Elec. Circuits Syst. (ICECS),
pp. 645648, Dec. 2007.

I. Vytyaz, D. Lee, P. Hanumolu, U. Moon, and K. Mayaram,
"Sensitivity analysis for oscillators,"
Int. Conf. ComputerAided Design (ICCAD),
pp. 458463, Nov. 2007.

J. Carnes, G. Ahn, and U. Moon,
"A 1V 10b 60MS/s hybrid
opampreset/switchedRC pipelined ADC,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 236239, Nov. 2007.

N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu,
and U. Moon,
"A 1.8V 36mW 11bit 80MS/s pipelined ADC
using capacitor and opamp sharing,"
IEEE Asian SolidState Circuits Conf. (ASSCC),
pp. 240243, Nov. 2007.

Y. Kook, J. Li, B. Lee, and U. Moon,
"Lowpower and highspeed pipelined ADC
using timealigned CDS technique,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 321324, Sep. 2007.

G. Ahn, M. Kim, P. Hanumolu, and U. Moon,
"A 1V 10b 30MSPS switchedRC pipelined ADC,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 325328, Sep. 2007.

M. Brownlee, P. Hanumolu, and U. Moon,
"A 3.2Gb/s oversampling CDR with improved
jitter tolerance,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 353356, Sep. 2007.

V. Kratyuk, P. Hanumolu, K. Mayaram, and U. Moon,
"A 0.6GHz to 2GHz digital PLL with wide
tracking range,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 305308, Sep. 2007.

P. Hanumolu, G. Wei, U. Moon, and K. Mayaram,
"Digitallyenhanced phaselocking circuits,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 361368, Sep. 2007.

T. Wu, P. Hanumolu, K. Mayaram, and U. Moon,
"A 4.2 GHz PLL frequency synthesizer with
an adaptively tuned coarse loop,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 547550, Sep. 2007.

V. Sharma, U. Moon, and G. Temes,
"Efficient pipelined ADCs using integer gain MDACs,"
IEEE PRIME,
pp. 14, Jul. 2007.

I. Vytyaz, D. Lee, S. Lu, A. Mehrotra, U. Moon, and K. Mayaram,
"Parameter finding methods for oscillators
withba specified oscillation frequency,"
Design Automation Conference (DAC),
pp. 424429, Jun. 2007.

S. Kwon and U. Moon,
"A highspeed deltasigma modulator with
relaxed DEM timing requirement,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 733736, May 2007.

B.R. Gregoire and U. Moon,
"Processindependent resistor
temperaturecoefficients using series/parallel and parallel/series
composite resistors,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 28262829, May 2007.

N. Maghari, S. Kwon, G. Temes, and U. Moon,
"Mixedorder sturdy MASH deltasigma
modulator,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 257260, May 2007.

I. Vytyaz, D. Lee, A. Mehrotra, U. Moon, and K. Mayaram,
"Periodic steadystate analysis of
oscillators with a specified oscillation frequency,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 10731076, May 2007.

P. Kurahashi, P. Hanumolu, G. Temes, and U. Moon,
"A 0.6V highly linear SwitchedRMOSFETC
filter,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 833836, Sep. 2006 (Best Student Paper Award).

P. Hanumolu, M. Kim, G. Wei, and U. Moon,
"A 1.6Gbps digital clock and data
recovery circuit,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 603606, Sep. 2006.

V. Kratyuk, P. Hanumolu, K. Ok, K. Mayaram, and U. Moon,
"A digital PLL with a stochastic
timetodigital converter,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 3839, Jun. 2006.

T. Wu, K. Mayaram, and U. Moon,
"An onchip calibration technique
for reducing supply voltage sensitivity in ring oscillators,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 128129, Jun. 2006.

P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon,
"A subpicosecond resolution 0.51.5GHz
digitaltophase converter,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 9293, Jun. 2006.

Q. Meng, K. Lee, T. Sugimoto, K. Hamashita, K. Takasuka, S. Takeuchi,
U. Moon, and G. Temes,
"A 0.8V 88dB dualchannel audio
deltasigma DAC with headphone driver,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 6667, Jun. 2006.

P. Hanumolu, G. Wei, and U. Moon,
"A wide tracking range 0.24Gbps clock
and data recovery circuit,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 8889, Jun. 2006.

G. Ahn, P. Hanumolu, M. Kim, S. Takeuchi1, T. Sugimoto1, K. Hamashita1,
K. Takasuka1, G. Temes, and U. Moon,
"A 12b 10MS/s pipelined ADC using
reference scaling,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 272273, Jun. 2006.

M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes,
and U. Moon,
"A 0.9V 92dB doublesampled switchedRC
deltasigma audio ADC,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 200201, Jun. 2006.

M. Kim, P. Hanumolu, and U. Moon,
"A 10MS/s 11b 0.19mm^{2}
algorithmic ADC with improved clocking,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 6061, Jun. 2006.

J. Carnes and U. Moon,
"The effect of switch resistance on
pipelined ADC MDAC settling time,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 52515254, May 2006.

T. Wu, U. Moon, and K. Mayaram,
"Dependence of LC VCO oscillation
frequency on bias current,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 50395042, May 2006.

N. Talebbeydokhti, P Hanumolu, P. Kurahashi, and U. Moon,
"Constant transconductance bias circuit
with an onchip resistor,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 28572860, May 2006.

M. Brownlee, P. Hanumolu, K. Mayaram,and U. Moon,
"A 0.5 to 2.5GHz PLL with fully differential
supplyregulated tuning,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 588589, Feb. 2006.

A. Nemmani, M. Vandepas, K. Ok, K. Mayaram, and U. Moon,
"Design techniques for radiation
hardened phase locked loops,"
Mil. Aero. Prog. Logic Dev. Int. Conf. (MAPLD),
Sep. 2005.

M. Vandepas, K. Ok, A. Nemmani, M. Brownlee, K. Mayaram, and U. Moon,
"Characterization of 1.2GHz phase locked
loops and voltage controlled oscillators in a total dose radiation
environment,"
Mil. Aero. Prog. Logic Dev. Int. Conf. (MAPLD),
Sep. 2005.

V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram,
"A low spur fractionalN frequency
synthesizer architecture,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 28072810, May 2005.

T. Wu, P. Hanumolu, U. Moon, and K. Mayaram,
"An FMDLL based dualloop frequency
synthesizer for 5GHz WLAN applications,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 39863989, May 2005.

V. Kratyuk, I. Vytyaz, U. Moon, and K. Mayaram,
"Analysis of supply and ground noise
sensitivity in ring and LC oscillators,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 59865989, May 2005.

V. Sharma, U. Moon, and G. Temes,
"A generic multilevel multiplying D/A
converter for pipelined ADCs,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 61826185, May 2005.

T. Rengachari, V. Sharma, G. Temes, and U. Moon,
"A 10bit algorithmic A/D converter for
Cytosensor Application,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 61866189, May 2005.

G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita,
K. Takasuka, G. Temes, and U. Moon,
"A 0.6V 82dB deltasigma audio ADC using
switchedRC integrators,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 166167, Feb. 2005.

X. Wang, Y. Guo, U. Moon, and G. Temes,
"Experimental verification of a
correlationbased correction algorithm for multibit deltasigma ADCs,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 523526, Oct. 2004.

G. Vemulapalli, P. Hanumolu, and U. Moon,
"A 0.8V accuratelytuned continuoustime
filter,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 4548, Oct. 2004.

C. Myers, J. Li, D. Chang, and U. Moon,
"Low voltage highSNR pipeline data
converters,"
IEEE Northeast Workshop Circuits Syst. (NEWCAS),
pp. 245248, Jun. 2004.

M. Brownlee, P. Hanumolu, U. Moon, and K. Mayaram,
"The effect of power supply noise on
ring oscillator phase noise,"
IEEE Northeast Workshop Circuits Syst. (NEWCAS),
pp. 225228, Jun. 2004.

J. Li, G. Ahn, D. Chang, and U. Moon,
"0.9V 12mW 2MSPS algorithmic ADC with
81dB SFDR,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 436439, Jun. 2004.

P. Hanumolu, B. Casper, R. Mooney, G. Wei, and U. Moon,
"Jitter in highspeed serial and
parallel links,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. IV, pp. 425428, May 2004.

S. Xiao, J. Silva, U. Moon, and G. Temes,
"A tunable dutycyclecontrolled
switchedRMOSFETC CMOS filter for lowvoltage and highlinearity
applications,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 433436, May 2004.

J. Silva, U. Moon, and G. Temes,
"Lowdistortion deltasigma topologies
for MASH architectures,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 11441147, May 2004.

M. Kim, G. Ahn, and U. Moon,
"An improved algorithmic ADC
clocking scheme,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 589592, May 2004.

J. Li and U. Moon,
"A 1.8V 67mW 10bit 100MSPS pipelined ADC using
timeshifted CDS technique,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 413416, Sep. 2003.

B. Greenley, R. Veith, D. Chang, and U. Moon,
"A 1.4V 10b CMOS DC DAC in 0.01mm^{2},"
IEEE Int. SOC Conf.,
pp. 237238, Sep. 2003.

M. Keskin, U. Moon, and G. Temes,
"A 0.9V 10.7MHz 3.6mW bandpass
modulator using unitygainreset opamps,"
IEEE Int. Workshop ADC Mod. Test.,
pp. 6366, Sep. 2003.

M. Keskin, U. Moon, and G. Temes,
"Amplifier imperfection effects in
switchedcapacitor resonators,"
IEEE Int. Workshop ADC Mod. Test.,
pp. 6770, Sep. 2003.

D. Chang and U. Moon,
"A 0.9V 9mW 1MSPS digitally calibrated ADC
with 75dB SFDR,"
IEEE Symp. VLSI Circuits (VLSI),
pp. 6770, Jun. 2003.

J. Li and U. Moon,
"An extended radixbased digital calibration
technique for multistage ADC,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 829832, May 2003.

A. Pulincherry, M. Hufford, E. Naviasky, and U. Moon,
"Continuoustime frequency translating
bandpass deltasigma modulator,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 10131016, May 2003.

D. Bruneau, A. Early, U. Moon, and G. Temes,
"Highspeed switchedcapacitor filters
based on unity gain buffer,"
IEEJ Int. Analog VLSI Workshop,
pp. 59, Sep. 2002.

M. Coe and U. Moon,
"Mismatchshaping successiveapproximation
ADC,"
IEEJ Int. Analog VLSI Workshop,
pp. 6064, Sep. 2002.

A. Rao, W. McIntyre, U. Moon, and G. Temes,
"A noiseshaped switchedcapacitor DCDC
voltage regulator,"
IEEE European SolidState Circuits Conf. (ESSCIRC),
pp. 375378, Sep. 2002.

X. Wang, P. Kiss, U. Moon, and G. Temes,
"Digital correlation technique for the
estimation and correction of DAC errors in multibit MASH deltasigma ADCs,"
Int. Conf. Advanced A/D D/A Conv. Tech. (ADDA),
pp. 3942, Jun. 2002.

M. Keskin, M. Brown, U. Moon, and G. Temes,
"A voltagemode switchedcapacitor bandpass
deltasigma modulator,"
Int. Conf. Advanced A/D D/A Conv. Tech. (ADDA),
pp. 1922 , Jun. 2002.

J. Li and U. Moon,
"Highspeed pipelined A/D converter using
timeshifted CDS technique,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 909912, May 2002.

A. Rao, W. McIntyre, J. Parry, U. Moon, and G. Temes,
"Buckboost switchedcapacitor DCDC
voltage regulator using deltasigma control loop,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. IV, pp. 743746, May 2002.

D. Chang and U. Moon,
"Radixbased digital calibration technique
for multistage ADC,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. II, pp. 796799, May 2002.

X. Wang, U. Moon, M. Liu, and G. Temes,
"Digital correlation technique for the
estimation and correction of DAC errors in multibit MASH deltasigma ADCs,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. IV, pp. 691694, May 2002.

D. Chang, L. Wu, and U. Moon,
"Lowvoltage pipelined ADC using
opampreset switching technique,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 461464, May 2002.

S. Yoo, T. Oh, J. Moon, S. Lee, and U. Moon,
"A 2.5V 10b 120MSamples/s CMOS pipelined
ADC with high SFDR,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 441444, May 2002.

J. Sonntag, J. Stonick, J. Gorecki, B. Beale, B. Check,
X. Gong, J. Guiliano, K. Lee, B. Lefferts, D. Martin, U. Moon, A. Sengir,
S. Titus, G. Wei, D. Weinlader, and Y. Yang,
"An adaptive PAM4 5Gb/s backplane
transceiver in 0.25um CMOS,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 363366, May 2002.

J. Silva, X. Wang, P. Kiss, U. Moon, and G. Temes,
"Digital techniques for improved deltasigma
data conversion,"
invited tutorial,
IEEE Custom Int. Circuits Conf. (CICC),
pp. 183190, May 2002.

M. Keskin, U. Moon, and G. Temes,
"A 1V 10MHz clockrate 13bit CMOS
deltasigma modulator using unitygainreset opamps,"
IEEE European SolidState Circuits Conf. (ESSCIRC),
pp. 532535, Sep. 2001.

B. Greenley, R. Veith, and U. Moon,
"A 1.8V CMOS DAC cell with ultra high
gain opamp in 0.0143mm^{2},"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 412415, May 2001.

R. Perigny, U. Moon, and G. Temes
"Area efficient CMOS charge pump
circuits,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 492495, May 2001.

M. Keskin, U. Moon, and G. Temes,
"Lowvoltage lowsensitivity
switchedcapacitor bandpass deltasigma modulator,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 348351, May 2001.

P. Kiss, U. Moon, J. Steensgaard, J. Stonick, and G. Temes,
"Multibit deltasigma ADC with mixedmode
DAC error correction,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 280283, May 2001.

T. Kajita, U. Moon, and G. Temes,
"A noiseshaping accelerometer interface
circuit for twochip implementation,"
IEEE Inst. Meas. Techology Conf.,
pp. 15811586, May 2001.

M. Keskin, U. Moon, and G. Temes,
"Lowvoltage switchedcapacitor resonators,"
IEEE Dallas CAS Workshop Low Power Voltage Circuits Syst.,
pp. 1922, March 2001.

Z. Zheng, B. Min, U. Moon, and G. Temes,
"Efficient errorcancelling algorithmic
ADC,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 451454, May 2000.

L. Wu, M. Keskin, U. Moon, and G. Temes,
" Efficient commonmode feedback circuits
for pseudodifferential switchedcapacitor stages,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. V, pp. 445448, May 2000.

U. Moon, J. Silva, J. Steensgaard, and G. Temes,
"A switchedcapacitor DAC with analog
mismatch correction,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. IV, pp. 421424, May 2000.

T. Kajita, U. Moon, and G. Temes,
"A noiseshaping accelerometer interface
circuit for twochip implementation,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. IV, pp. 337340, May 2000.

P. Kiss, J. Silva, U. Moon, J. Stonick, and G. Temes,
"Improved adaptive digital compensation
for cascaded deltasigma ADCs,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. II, pp. 3336, May 2000.

M. Lehne, J. Stonick, and U. Moon,
"An adaptive offset cancellation mixer for
direct conversion receivers in 2.4GHz CMOS,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. I, pp. 319322, May 2000.

U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard,
and F. Maloberti,
"Switchedcapacitor circuit techniques in
submicron lowvoltage CMOS,"
IEEE Int. Conf. VLSI CAD,
pp. 349358, Oct. 1999.

G. Temes, U. Moon, and J. Steensgaard,
"Analog (s)witchcraft, or how to perform accurate
and linear data conversion using inaccurate nonlinear elements,"
IEEE Elec. Circuits Syst. Conf.,
pp. 97101, Sep. 1999.

J. Steensgaard, U. Moon, and G. Temes,
"Mismatchshaping serial digitaltoanalog
converter,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. II, pp. 58, May 1999.

Z. Zheng, U. Moon, J. Steensgaard, B. Wang, and G. Temes,
"Capacitor mismatch error cancellation
technique for a successiveapproximation A/D converter,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. II, pp. 326329, May 1999.

E. Bidari, M. Keskin, F. Maloberti, U. Moon, J. Steensgaard, and G. Temes,
"Lowvoltage switchedcapacitor circuits,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
vol. II, pp. 4952, May 1999.

J. Steensgaard, U. Moon, and G. Temes,
"Mismatchshaped pseudopassive
twocapacitor DAC,"
IEEE Alessandro Volta Workshop on LowPower Design,
pp. 144152, March 4, 1999.

U. Moon, A. Mastrocola, J. Alsayegh, and S. Werner,
"Timing recovery in CMOS using nonlinear
spectralline method,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 1316, May 1996.

R. Shariadoust, K. Lakshmikumar, U. Moon, H.S. Fetterman,
M. Sankaran, D. Sherry, J. Kumar, and S. Daubert,
"A highspeed, highresolution analog front
end for digital subscriber line applications,"
IEEE Custom Int. Circuits Conf. (CICC),
pp. 289292, May 1995.

U. Moon and B. Song,
"Lowdistortion continuoustime RMOSFETC
filters,"
IEEE Int. Symp. Circuits Syst. (ISCAS),
pp. 11681171, May 1993.

U. Moon and B. Song,
"A lowdistortion 22kHz 5thorder Bessel
filter,"
IEEE Int. SolidState Circuits Conf. (ISSCC),
pp. 110111, Feb. 1993.
Graduate Thesis
Journal Papers
Conference Papers
Miscellaneous

Allen Waters,
"Automated Verilogtolayout synthesis of ADCs using custom analog cells,"
Ph.D. Dissertation, Oregon State University, 2015.

Brandilyn Coker,
"Limitations and optimization of a blind calibration algorithm for
nonlinearity in analog to digital converters,"
M.S. Thesis, Oregon State University, 2015.

Farshad Farahbakhshian,
"Dynamic biasing for ring amplification,"
M.S. Thesis, Oregon State University, 2014.

Jerry Leung,
"Data driven optimization in SAR ADC,"
M.S. Thesis, Oregon State University, 2014.

Yue Hu,
"Efficient use of time information in analogtodigital converters,"
Ph.D. Dissertation, Oregon State University, 2014.

Taehwan Oh,
"Power efficient analogtodigital converters using both voltage and time
domain information,"
Ph.D. Dissertation, Oregon State University, 2013.

Hariprasath Venkatram,
"Energy and area efficient techniques for data converters,"
Ph.D. Dissertation, Oregon State University, 2013.

Manideep Gande,
"Design techniques for time based data converters,"
Ph.D. Dissertation, Oregon State University, 2013.

Jon Guerber,
"Time and statistical information utilization in high efficiency
sub‐micron CMOS successive approximation analog to digital converters,"
Ph.D. Dissertation, Oregon State University, 2012.

Ben Hershberg
"Ring amplification for switched capacitor circuits,"
Ph.D. Dissertation, Oregon State University, 2012.

HoYoung Lee
"Powerefficient twostep pipelined analogtodigital conversion,"
Ph.D. Dissertation, Oregon State University, 2011.

Omid Rajaee,
"Design of low OSR, high precision analogtodigital converters,"
Ph.D. Dissertation, Oregon State University, 2010.

Skyler Weaver,
"Automated synthesis of analog to digital conversion,"
Ph.D. Dissertation, Oregon State University, 2010.

Tawfiq Musah,
"Low power design techniques for analogtodigital converters in submicron
CMOS,"
Ph.D. Dissertation, Oregon State University, 2010.

Nima Maghari,
"Architectural compensation techniques for analog inaccuracies in
deltasigma analogtodigital converters,"
Ph.D. Dissertation, Oregon State University, 2010.

Peter Kurahashi,
"Dutycycle controlled switched resistor techniques for continuously tunable,
lowvoltage circuits,"
Ph.D. Dissertation, Oregon State University, 2009.

Sunwoo Kwon,
"A multibit hybrid DSM over fullscale range without feedback DEM,"
Ph.D. Dissertation, Oregon State University, 2009.

Naga Sasidhar Lingam,
"Low power design techniques for high speed pipelined ADCs,"
Ph.D. Dissertation, Oregon State University, 2009.

Rob Gregoire,
"Correlated level shifting as a powersaving method to reduce the effects of finite DC gain and signal swing in opamps,"
Ph.D. Dissertation, Oregon State University, 2008.

David Gubbins,
"Continuous time input pipeline ADCs,"
Ph.D. Dissertation, Oregon State University, 2008.

Igor Vytyaz,
"Automated analysis, design, and optimization of low noise oscillators,"
Ph.D. Dissertation, Oregon State University, 2008.

Aaron Caffee,
(Referenceless linear oscillators),
M.S. Project, Oregon State University, 2007.

Xueqiang Ding,
(Frequency synthesizers for communication applications),
M.S. Project, Oregon State University, 2007.

Joshua Carnes,
"Low voltage techniques for pipelined analogtodigital converters,"
M.S. Thesis, Oregon State University, 2007.

Ting Wu,
"Design techniques for PVT tolerant phaselocked loops,"
Ph.D. Dissertation, Oregon State University, 2007.

Volodymyr Kratyuk,
"Digital PLLs for multiGHz clock generation,"
Ph.D. Dissertation, Oregon State University, 2006.

Merrick Brownlee,
"Low noise clocking for high speed serial links,"
Ph.D. Dissertation, Oregon State University, 2006.

Pavan Hanumolu,
"Design techniques for clocking high performance signaling systems,"
Ph.D. Dissertation, Oregon State University, 2006.

Erik Geissenhainer,
"Characterization of a digital phase locked loop and a stochastic time to
digital converter,"
M.S. Thesis, Oregon State University, 2006.

Mingyu Kim,
"Lowpower design technicuqes for lowvoltage analogtodigital converters,"
Ph.D. Dissertation, Oregon State University, 2006.

Yue Zhang,
(Continuoustime deltasigma modulator),
M.S. Project, Oregon State University, 2005.

Matthew Brown,
"Noise optimization of lowvoltage CMOS audio preamplifier systems,"
M.S. Thesis, Oregon State University, 2005.

GilCho Ahn,
"Design techniques for lowvoltage and lowpower analogtodigital converters,"
Ph.D. Dissertation, Oregon State University, 2005.

Kerem Ok,
"A stochastic timetodigital converter for
digital phaselocked loops,"
M.S. Thesis, Oregon State University, 2005.

Martin Vandepas,
"Oscillators and phase locked loops for
space radiation environments,"
M.S. Thesis, Oregon State University, 2005.

Anantha Nag Nemmani,
"Design techniques for radiation
hardened phaselocked loops,"
M.S. Thesis, Oregon State University, 2005.

Jacob Zechmann,
"Investigation of a noiseshaping
accelerometer interface circuit for twochip implementation,"
M.S. Thesis, Oregon State University, 2005.

Charlie Myers,
"Design of highperformance pipeline
analogtodigital converters in lowvoltage processes,"
M.S. Thesis, Oregon State University, 2005.

John Bennett,
"Implications of jitter on high speed
serial interface standards, simulation, and design,"
M.S. Project, Oregon State University, 2004.

Jose Silva,
"Highperformance deltasigma
analogtodigital data converters,"
Ph.D. Dissertation, Oregon State University, 2004.

Vivek Sharma,
"Generalized radix design techniques for
lowpower, lowvoltage pipelined & cyclic analogdigital converters,"
M.S. Thesis, Oregon State University, 2004.

Yuhua Guo,
"A study of basic building blocks of analogtodigital deltasigma modulators,"
M.S. Thesis, Oregon State University, 2004.

Thirumalai Rengachari,
"A 10 bit algorithmic A/D
converter for a biosensor,"
M.S. Thesis, Oregon State University, 2004.

Ying Xiao,
"A tunable dutycyclecontrolled
switchedRMOSFETC CMOS filter for lowvoltage and highlinearity
applications,"
M.S. Thesis, Oregon State University, 2004.

David Stoops,
(Simulating switched capacitor circuits with SpectreRF),
M.S. Project, Oregon State University, 2003.

Kiseok Yoo,
"Opampfree SC biquad LPF and
deltasigma ADC,"
M.S. Thesis, Oregon State University, 2003.

Xuesheng Wang,
"A fully digital technique for the
estimation and correction of the DAC error in multibit deltasigma ADCs,"
Ph.D. Dissertation, Oregon State University, 2003.

Gowtham Vemulapalli,
"Accurately tunable lowvoltage
continuoustime filter,"
M.S. Thesis, Oregon State University, 2003.

Jipeng Li,
"Accuracy enhancement techniques in
lowvoltage highspeed pipelined ADC design,"
Ph.D. Dissertation, Oregon State University, 2003.

Eashwar Thiagarajan,
(Low voltage filter),
M.S. Project, Oregon State University, 2003.

Ranganathan Desikachari,
"Highspeed CMOS dualmodulus
prescalers for frequency synthesis,"
M.S. Thesis, Oregon State University, 2003.

Eric Wyers,
(LC oscillator),
M.S. Project, Oregon State University, 2003.

Mingliang Liu,
(Oversampling data converter),
M.S. Project, Oregon State University, 2003.

Mengzhe Ma,
"Design of high efficiency stepdown
switchedcapacitor DC/DC converter,"
M.S. Thesis, Oregon State University, 2003.

Anurag Pulincherry,
"A continuous time frequency
translating delta sigma modulator,"
M.S. Thesis, Oregon State University, 2002.

Dongyoung Chang,
"Design techniques for lowvoltage
analogtodigital converter,"
Ph.D. Dissertation, Oregon State University, 2002.

Charlie Yun,
"20stage pipelined ADC with radixbased
calibration,"
M.S. Thesis, Oregon State University, 2002.

Vinay Ramyead,
(CMOS prescaler),
M.S. Project, Oregon State University, 2002.

Arun Rao,
"An efficient switched capacitor buckboost
voltage regulator
using deltasigma control loop,"
M.S. Thesis, Oregon State University, 2002.

David Bruneau,
"Highspeed switchedcapacitor filters
based on unitygain buffers,"
M.S. Thesis, Oregon State University, 2002.

Matthew Coe,
"Digital implementation of a mismatchshaping
successiveapproximation ADC,"
M.S. Thesis, Oregon State University, 2001.

Daniel Thomas
"Fast opampfree delta sigma modulator,"
M.S. Thesis, Oregon State University, 2001.

Mustafa Keskin,
"Low voltage switched capacitor circuits
for lowpass and bandpass converters,"
Ph.D. Dissertation, Oregon State University, 2001.

Brandon Greenley,
"Area efficient D/A converter for
accurate DC operation,"
M.S. Thesis, Oregon State University, 2001.

Ryan Perigny,
"Area efficiency improvement of CMOS charge
pump circuits,"
M.S. Thesis, Oregon State University, 2000.

Jianping Wen,
"Error canceling lowvoltage SAR ADC,"
M.S. Thesis, Oregon State University, 2000.

Peter Kiss,
"Adaptive digital compensation of analog circuit
imperfections for cascaded deltasigma analogtodigital converters,"
Ph.D. Dissertation, 1999.

Lei Wu,
"Lowvoltage pipeline A/D converter,"
M.S. Thesis, Oregon State University, 1999.

Zhiliang Zheng,
"Low power high resolution data
converter in digital CMOS technology,"
M.S. Thesis, Oregon State University, 1999.

Emad Bidari,
"Lowvoltage switchedcapacitor circuits,"
M.S. Thesis, Oregon State University, 1998.

UnKu Moon,
"Linearity improvement technique for CMOS
continuoustime filters,"
Ph.D. Dissertation, University of Illinois, UrbanaChampaign, 1994.
Miscellaneous
Journal Papers
Conference Papers
Graduate Thesis

A. Waters,
"SOCCER
Rematch expands field to five schools,"
IEEE SolidState Circuits Magazine,
vol. 6, no. 4, pp. 6374, 2014

D. Adams,
"Murmann,
Moon, and grad students square off at Mt. Shasta for circuits and
soccer contest,"
IEEE SolidState Circuits Magazine,
vol. 5, no. 4, pp. 4344, 2013

P. Hanumolu and U. Moon,
"Shannon
limit of collegiality,"
IEEE SolidState Circuits Magazine,
vol. 5, no. 2, pp. 14, 2013

S. Noall,
"SSCSUtah
chapter kickoff meeting,"
IEEE SolidState Circuits Magazine,
vol. 4, no. 2, pp. 7275, 2012

U. Moon,
"SSCS
pastpresident and JSSC editorinchief takes a hike,"
IEEE SolidState Circuits Magazine,
vol. 4, no. 1, pp. 57, 2012

K. Olstein,
"DL
UnKu Moon delivers DL talks across the United States and Canada on
emerging ADCs,"
IEEE SolidState Circuits Magazine,
vol. 3, no. 1, pp. 7576, 2012

U. Moon and K. Nagaraj,
"ISSCC
2006 panel on classic circuits,"
IEEE SolidState Circuits Society Newsletter,
vol. 11, no. 2, pp. 11, 2006